Datasheet

LTM4603HV
14
4603hvf
to the rising edge of the external clock. The frequency
range is ±30% around the operating frequency of 1MHz.
A pulse detection circuit is used to detect a clock on the
PLLIN pin to turn on the phase lock loop. The pulse width
of the clock has to be at least 400ns and 2V in amplitude.
During the start-up of the regulator, the phase-lock loop
function is disabled.
INTV
CC
and DRV
CC
Connection
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV
CC
for driving the internal power MOSFETs. Therefore, if the
system does not have a 5V power rail, the LTM4603HV
can be directly powered by Vin. The gate driver current
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
P
LDO_LOSS
= 20mA • (V
IN
– 5V)
The LTM4603HV also provides the external gate driver
voltage pin DRV
CC
. If there is a 5V rail in the system, it is
recommended to connect DRV
CC
pin to the external 5V
rail. This is especially true for higher input voltages. Do
not apply more than 6V to the DRV
CC
pin. A 5V output can
be used to power the DRV
CC
pin with an external circuit
as shown in Figure 18.
Parallel Operation of the Module
The LTM4603HV device is an inherently current mode
controlled device. Parallel modules will have very good
current sharing. This will balance the thermals on the
design. The voltage feedback equation changes with the
variable n as modules are paralleled:
VV
k
n
R
R
OUT
SET
SET
=
+
06
60 4
.
.
n is the number of paralleled modules.
Thermal Considerations and Output Current Derating
The power loss curves in Figures 7 and 8 can be used
in coordination with the load current derating curves in
Figures 9 to 12, and Figures 13 to 16 for calculating an
approximate θ
JA
for the module with various heat sinking
methods. Thermal models are derived from several tem-
perature measurements at the bench and thermal modeling
analysis. Thermal Application Note 103 provides a detailed
explanation of the analysis for the thermal models and the
derating curves. Tables 3 and 4 provide a summary of the
equivalent θ
JA
for the noted conditions. These equivalent
θ
JA
parameters are correlated to the measured values,
and are improved with air fl ow. The case temperature is
maintained at 100°C or below for the derating curves.
This allows for 4W maximum power dissipation in the
total module with top and bottom heatsinking, and 2W
power dissipation through the top of the module with an
approximate θ
JC
between 6°C/W to 9°C/W. This equates
to a total of 124°C at the junction of the device.
APPLICATIO S I FOR ATIO
WUU
U
Figure 7. 1.5V Power Loss
Figure 8. 3.3V Power Loss
Figure 9. No Heat Sink
OUTPUT CURRENT (A)
0
2.0
2.5
35
4603HV F07
1.5
1.0
12
467
0.5
0
POWER LOSS (W)
12V LOSS
5V LOSS
OUTPUT CURRENT (A)
0
2.0
2.5
3.5
35
4603HV F08
1.5
1.0
12
467
0.5
0
3.0
POWER LOSS (W)
24V LOSS
12V LOSS
AMBIENT TEMPERATURE (°C)
75
0
MAXIMUM LOAD CURRENT (A)
1
2
3
4
5
6
80 85 90 95
4603HV F09
5V
IN
, 1.5V
OUT
, 0LFM
5V
IN
, 1.5V
OUT
, 200LFM
5V
IN
, 1.5V
OUT
, 400LFM