Datasheet

LTM4603HV
10
4603hvf
APPLICATIO S I FOR ATIO
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The typical LTM4603HV application circuit is shown in
Figure 20. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 2 for specifi c external capacitor
requirements for a particular application.
V
IN
to V
OUT
Step-Down Ratios
There are restrictions in the maximum V
IN
and V
OUT
step
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
Characteristics curves labeled V
IN
to V
OUT
Step-Down
Ratio. Note that additional thermal derating may apply. See
the Thermal Considerations and Output Current Derating
section of this data sheet.
Output Voltage Programming and Margining
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 1M and a 60.4k 0.5%
internal feedback resistor connects V
OUT
and V
FB
pins
together. The V
OUT_LCL
pin is connected between the 1M
and the 60.4k resistor. The 1M resistor is used to protect
against an output overvoltage condition if the V
OUT_LCL
pin is not connected to the output, or if the remote sense
amplifi er output is not connected to V
OUT_LCL
. The output
voltage will default to 0.6V. Adding a resistor R
SET
from
the V
FB
pin to SGND pin programs the output voltage:
VV
kR
R
OUT
SET
SET
=
+
06
60 4
.
.
Table 1. Standard 1% Resistor Values
R
SET
(kΩ)
Open 60.4 40.2 30.1 25.5 19.1 13.3 8.25
V
OUT
(V)
0.6 1.2 1.5 1.8 2 2.5 3.3 5
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference ±
offset for margining. A 1.18V reference divided by the
R
PGM
resistor on the MPGM pin programs the current.
Calculate V
OUT(MARGIN)
:
V
V
V
OUT MARGIN
OUT
OUT()
%
•=
100
where %V
OUT
is the percentage of V
OUT
you want to margin,
and V
OUT(MARGIN)
is the margin quantity in volts:
R
V
V
V
V
k
PGM
OUT
OUT MARGIN
=
06
118
10
.
•
.
•
()
where R
PGM
is the resistor value to place on the MPGM
pin to ground.
The output margining will be ± margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:
MARG0 MARG1 MODE
LOW LOW NO MARGIN
LOW HIGH MARGIN UP
HIGH LOW MARGIN DOWN
HIGH HIGH NO MARGIN
Input Capacitors
LTM4603HV module should be connected to a low AC
impedance DC source. Input capacitors are required to
be placed adjacent to the module. In Figure 20, the 10μF
ceramic input capacitors are selected for their ability to
handle the large RMS current into the converter. An input
bulk capacitor of 100μF is optional. This 100μF capacitor is
only needed if the input source impedance is compromised
by long inductive leads or traces.
For a buck converter, the switching duty-cycle can be
estimated as:
D
V
V
OUT
IN
=
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
I
I
DD
CIN RMS
OUT MAX
()
()
%
••–=
()
η
1
In the above equation, η% is the estimated effi ciency of
the power module. C
IN
can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitor. Note the capacitor ripple current rat-
ings are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,