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ManualsBrandsLinear Technology ManualsDAC - Digital to AnalogVideo Encoder 10bit LFCSP-
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Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 97 of 107
Table 90. 10-Bit 625i YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xC1 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
0x88 0x10 10-bit input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 91. 16-Bit 625i YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xC1 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 92. 16-Bit 625i YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xC1 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 93. 16-Bit 625i RGB In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xC1 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
0x87 0x80 RGB input enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 94. 16-Bit 625i RGB In, CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xC3 Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled.
0x87 0x80 RGB input enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
0x8C 0xCB Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL mode (27 MHz input clock).
0x8D 0x8A
0x8E 0x09
0x8F 0x2A
Table 95. 16-Bit 625i RGB In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x80 0x11 PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
0x82 0xC1 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
0x87 0x80 RGB input enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
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