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ManualsBrandsLinear Technology ManualsDAC - Digital to AnalogVideo Encoder 10bit LFCSP-
919293949596979899100
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 94 of 107
Table 71. 10-Bit 525i YCrCb In, CVBS/Y-C Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xCB Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal enabled.
0x88 0x10 10-bit input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 72. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x80 0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88 0x10 10-bit input enabled.
Table 73. 10-Bit 525i YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x80 0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88 0x10 10-bit input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 74. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A 0x0C
Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 75. 16-Bit 525i YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset
0x00 0x1C All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x80 0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88 0x10 16-bit RGB input enabled.
0x8A
0x0C
Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
Table 76. 16-Bit 525i RGB In, YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (16×).
0x01 0x00 SD input mode.
0x80 0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82 0xC9 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x87 0x80 RGB input enabled.
0x88
0x10
16-bit RGB input enabled.
0x8A 0x0C Timing Mode 2 (slave).
HSYNC
/
VSYNC
synchronization.
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