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ManualsBrandsLinear Technology ManualsDAC - Digital to AnalogVideo Encoder 10bit LFCSP-
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ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 84 of 107
Cb
PIXE
L
D
ATA
HSYNC
VSYNC
PA
L = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
PA
L
= 864 × CLOCK/2
NTSC = 858 × CLOCK/2
Cb
Y
Y
Cr
06234-112
Figure 114. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 accept or generates horizontal synchronization and odd/even field signals.
When
HSYNC
is high, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7390/ADV7391/ADV7392/
ADV7393 automatically blank all normally blank lines as required by the CCIR-624 standard.
HSYNC
and
VSYNC
are output in master
mode and input in slave mode on the
HSYNC
and
VSYNC
pins, respectively.
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
283
284
285
ODD FIELD EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
522 523 524 525
9
10 11
20 21 22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
HSYNC
FIELD
HSYNC
FIELD
8
765
4
32
1
06234-113
Figure 115. SD Timing Mode 3, NTSC
622 623 624 625
5
6
21 22 23
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
FIELD
DISPLAY
309 310 311 312 313 314 315 316
317
318 319
334 335 336
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
FIELD
DISPLAY
320
4
32
1
7
HSYNC
HSYNC
06234-114
Figure 116. SD Timing Mode 3, PAL
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