Datasheet
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 83 of 107
522 523 524 525
9
10 11
20 21 22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
5
7
6
4
3
2
1
8
HSYNC
VSYNC
HSYNC
VSYNC
06234-109
Figure 111. SD Timing Mode 2, Slave Option, NTSC
622 623 624
625
21 22
23
DISPL
AY
VERTICA
L BLANK
ODD FIELD
EVEN FIELD
DISPLAY
309
310 311
312 313 314
315 316
317
318
319
334
335 336
DISPL
AY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPL
AY
320
765
4
3
2
1
HSYNC
VSYNC
HSYNC
VSYNC
06234-110
Figure 112. SD Timing Mode 2, Slave Option, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 can generate horizontal and vertical synchronization signals. A coincident
low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high
indicates the start of an even field. The
ADV7390/ADV7391/ADV7392/ADV7393 automatically blank all normally blank lines as required
by the CCIR-624 standard.
HSYNC
and
VSYNC
are output on the
HSYNC
and
VSYNC
pins, respectively.
Cb
Y
PIXEL
DATA
HSYNC
VSYNC
PAL = 132
× CLOCK/2
NTSC = 122 × CLOCK/2
Y
Cr
06234-111
Figure 113. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
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