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ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 80 of 107
SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV7390/ADV7391/ADV7392/ADV7393 are controlled by the SAV (start of active video) and EAV (end of active video) time codes
embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is
sent immediately before and after each line during active picture and retrace. If the
VSYNC
and
HSYNC
pins are not used, they should be
tied to V
DD_IO
when using this mode.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
Y
C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
06234-102
Figure 104. SD Timing Mode 0, Slave Option
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV7390/ADV7391/ADV7392/ADV7393 generate H and F signals required for the SAV and EAV time codes in the CCIR-656
standard. The H bit is output on
HSYNC
and the F bit is output on
VSYNC
.
522 523 524 525
8
9
10 11 20 21
22
DISPLAY
DISPL
AY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
H
F
260 261 262
263 264 265 266 267 268 269
270 271 272 273 274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
H
F
765
4
32
1
06234-103
Figure 105. SD Timing Mode 0, Master Option, NTSC
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