Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 71 of 107
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 10 nF and 0.1 μF ceramic capacitors. The V
AA
, PV
DD
,
V
DD_IO
, and both V
DD
pins should be individually decoupled to
ground. The decoupling capacitors should be placed as close as
possible to the ADV7390/ADV7391/ADV7392/ADV7393 with
the capacitor leads kept as short as possible to minimize lead
inductance.
A 1 μF tantalum capacitor is recommended across the V
AA
supply in addition to the 10 nF and 0.1 μF ceramic capacitors.
Power Supply Sequencing
The ADV7390/ADV7391/ADV7392/ADV7393 are robust to all
power supply sequencing combinations. Any sequence can be
used. However, all power supplies should settle to their nominal
voltages within one second.
Digital Signal Interconnect
The digital signal traces should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal traces should not overlay the V
AA
or PV
DD
power plane.
Due to the high clock rates used, avoid long clock traces to the
ADV7390/ADV7391/ADV7392/ADV7393 to minimize noise
pickup.
Any pull-up termination resistors for the digital inputs should
be connected to the V
DD_IO
power supply.
Analog Signal Interconnect
DAC output traces should be treated as transmission lines with
appropriate measures taken to ensure optimal performance (for
example, impedance matched traces). The DAC output traces
should be kept as short as possible. The termination resistors on
the DAC output traces should be placed as close as possible to,
and on the same side of the PCB as, the ADV7390/ADV7391/
ADV7392/ADV7393.
To avoid crosstalk between the DAC outputs, it is recommended
that as much space as possible be left between the traces
connected to the DAC output pins. Adding ground traces
between the DAC output traces is also recommended.
ADDITIONAL LAYOUT CONSIDERATIONS FOR THE
WLCSP PACKAGE
Due to the high pad density and 0.5 mm pitch of the WLCSP, it
is not recommended that connections to inner bumps be routed
on the top PCB layer only.
The traces (track and space) must fit within the limits of the
solder mask openings. Routing all traces on the top surface
layer of the board, while possible, is usually not a feasible
solution due to the limitations of the geometries imposed by
the board fabrication technology. Given a pitch of 0.5 mm with
a typical solder mask opening diameter of 0.35 mm, there is only
a 0.15 mm distance between the solder mask openings.
An alternative to routing on the top surface is to route out on
buried layers. To achieve this, the pads are connected to the
lower layers using microvias. See the AN-617 Application Note,
MicroCSP Wafer Level Chip Scale Package for additional details
about the board layout for the WLCSP package.
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