Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 7 of 107
SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications T
MIN
to T
MAX
(−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
SUPPLY VOLTAGES
V
DD
1.71 1.8 1.89 V
V
DD_IO
1.71 3.3 3.63 V
PV
DD
1.71 1.8 1.89 V
V
AA
2.6 3.3 3.465 V
POWER SUPPLY REJECTION RATIO 0.002 %/%
INPUT CLOCK SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V, PV
DD
= 1.71 V to 1.89 V, V
AA
= 2.6 V to 3.465 V, V
DD_IO
= 1.71 V to 3.63 V. All specifications T
MIN
to T
MAX
(−40°C
to +85°C), unless otherwise noted.
Table 4.
Parameter Conditions
1
Min Typ Max Unit
f
CLKIN
SD/ED 27 MHz
ED (at 54 MHz) 54 MHz
HD 74.25 MHz
CLKIN High Time, t
9
40 % of one clock cycle
CLKIN Low Time, t
10
40 % of one clock cycle
CLKIN Peak-to-Peak Jitter Tolerance 2 ±ns
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
ANALOG OUTPUT SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V, PV
DD
= 1.71 V to 1.89 V, V
AA
= 2.6 V to 3.465 V, V
DD_IO
= 1.71 V to 3.63 V. All specifications T
MIN
to T
MAX
(−40°C
to +85°C), unless otherwise noted.
Table 5.
Parameter Conditions Min Typ Max Unit
Full-Drive Output Current R
SET
= 510 Ω, R
L
= 37.5 Ω 33 34.6 37 mA
All DACs enabled
R
SET
= 510 Ω, R
L
= 37.5 Ω 31.5 33.5 37 mA
DAC 1 enabled only
1
Low-Drive Output Current R
SET
= 4.12 kΩ, R
L
= 300 Ω 4.3 mA
DAC-to-DAC Matching
DAC 1, DAC 2, DAC 3
2.0
%
Output Compliance, V
OC
0 1.4 V
Output Capacitance, C
OUT
10 pF
Analog Output Delay
2
6 ns
DAC Analog Output Skew DAC 1, DAC 2, DAC 3 1 ns
1
The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
2
Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
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