Datasheet
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 67 of 107
PIXEL AND CONTROL PORT READBACK
Subaddress 0x13, Subaddress 0x14, Subaddress 0x16
The ADV7390/ADV7391/ADV7392/ADV7393 support the
readback of most digital inputs via the I
2
C MPU port. This
feature is useful for board-level connectivity testing with
upstream devices.
The pixel port (P[15:0] or P[7:0]),
HSYNC
,
VSYNC
, and SFL
are available for readback via the MPU port. The readback
registers are located at Subaddress 0x13, Subaddress 0x14, and
Subaddress 0x16.
When using this feature, apply a clock signal to the CLKIN pin
to register the levels applied to the input pins. The SD input
mode (Subaddress 0x01, Bits[6:4] = 000) must be selected when
using this feature.
RESET MECHANISMS
Subaddress 0x17, Bit 1
A hardware reset is activated with a high-to-low transition on
the
RESET
pin in accordance with the timing specifications.
This resets all registers to their default values. After a hardware
reset, the MPU port is configured for I
2
C operation. For correct
device operation, a hardware reset is necessary after power-up.
The ADV7390/ADV7391/ADV7392/ADV7393 also have a
software reset accessible via the I
2
C MPU port. A software reset
is activated by writing a 1 to Subaddress 0x17, Bit 1. This resets
all registers to their default values. This bit is self-clearing; that
is, after a 1 has been written to the bit, the bit automatically
returns to 0.
A hardware reset is necessary after power-up for correct device
operation. If no hardware reset functionality is required by the
application, the
RESET
pin can be connected to an RC network
to provide the hardware reset necessary after power-up. After
power-up, the time constant of the RC network holds the
RESET
pin low long enough to cause a reset to take place. All
subsequent resets can be done via software.
SD TELETEXT INSERTION
Subaddress 0xC9 to Subaddress 0xCE
The ADV7390/ADV7391/ADV7392/ADV7393 support the
insertion of teletext data, using a two pin interface, when
operating in PAL mode. Teletext insertion is enabled using
Subaddress 0xC9, Bit 0.
In accordance with the PAL WST teletext standard, teletext data
should be inserted into the ADV7390/ADV7391/ADV7392/
ADV7393 at a rate of 6.9375 Mbps. On the ADV7390/ADV7391,
the teletext data is inserted on the
VSYNC
pin. On the
ADV7392/ADV7393, the teletext data can be inserted on the
VSYNC
or P0 pin (selectable through Subaddress 0xC9, Bit 2).
When teletext insertion is enabled, a teletext request signal is
output from the ADV7390/ADV7391/ADV7392/ADV7393 to
indicate when teletext data should be inserted. The teletext
request signal is output on the SFL pin. The position (relative to
the teletext data) and width of the request signal are
configurable using Subaddress 0xCA. The request signal can
operate in either a line or bit mode. The request signal mode is
controlled using Subaddress 0xC9, Bit 1.
To accou nt for the noninteger relationship between the teletext
insertion rate (6.9375 Mbps) and the pixel clock (27 MHz),
a teletext insertion protocol is implemented in the ADV7390/
ADV7391/ADV7392/ADV7393. At a rate of 6.9375 Mbps, the
time taken for the insertion of 37 teletext bits equates to 144
pixel clock cycles (at 27 MHz). For every 37 teletext bits
inserted into the ADV7390/ADV7391/ADV7392/ADV7393,
the 10
th
, 19
th
, 28
th
, and 37
th
bits are carried for three pixel clock
cycles, and the remainder are carried for four pixel clock cycles
(totaling 144 pixel clock cycles). The teletext insertion protocol
repeats every 37 teletext bits or 144 pixel clock cycles until all 360
teletext bits are inserted.
06234-143
ADDRESS AND DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
Figure 85. Teletext VBI Line
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