Datasheet
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 65 of 107
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV7390/ADV7391/ADV7392/ADV7393 are able to accept either EAV/SAV time codes
embedded in the input pixel data or external synchronization signals provided on the
HSYNC
and
VSYNC
pins (see Table 53). It is also
possible to output synchronization signals on the
HSYNC
and
VSYNC
pins (see Table 54 to Table 56).
Table 53. Timing Synchronization Signal Input Options
Signal Pin Condition
SD
HSYNC
In
HSYNC
SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0])
1
SD
VSYNC
/FIELD In
VSYNC
SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0])
1
ED/HD
HSYNC
In
HSYNC
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
ED/HD
VSYNC
/FIELD In
VSYNC
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
1
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 54. Timing Synchronization Signal Output Options
Signal Pin Condition
SD
HSYNC
Out
HSYNC
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)
1
SD
VSYNC
/FIELD Out
VSYNC
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)
1
ED/HD
HSYNC
Out
HSYNC
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
2
ED/HD
VSYNC
/FIELD Out
VSYNC
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)
2
1
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
2
ED/HD timing synchronization inputs must also be disabled; that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).
Table 55.
HSYNC
Output Control
1, 2
ED/HD Input Sync Format
(Subaddress 0x30,
Bit 2)
ED/HD
HSYNC Control
(Subaddress 0x34,
Bit 1)
ED/HD Sync
Output Enable
(Subaddress 0x02,
Bit 7)
SD Sync
Output Enable
(Subaddress 0x02,
Bit 6)
Signal on
HSYNC Pin
Duration
X X 0 0 Tristate N/A
X X 0 1
Pipelined SD
HSYNC
See the SD Timing
section.
0 0 1 X
Pipelined ED/HD
HSYNC
As per
HSYNC
timing.
1 0 1 X
Pipelined ED/HD
HSYNC
based on AV Code H bit
Same as line
blanking interval.
X 1 1 X
Pipelined ED/HD
HSYNC
based on horizontal
counter
Same as embedded
HSYNC
.
1
In all ED/HD standards where there is an
HSYNC
output, the start of the
HSYNC
pulse is aligned with the falling edge of the embedded
HSYNC
in the output video.
2
X = don’t care.
Table 56.
VSYNC
Output Control
1, 2
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
ED/HD
VSYNC
Control
(Subaddress
0x34, Bit 2)
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
SD Sync
Output Enable
(Subaddress
0x02, Bit 6)
Video Standard
Signal on
VSYNC Pin
Duration
x x 0 0 x Tristate N/A
x x 0 1 Interlaced
Pipelined SD
VSYNC
/field
See the SD Timing
section.
0 0 1 x x
Pipelined ED/HD
VSYNC
or field signal
As per
VSYNC
or
field signal timing.
1 0 1 x All HD interlaced
standards
Pipelined field signal
based on AV Code F bit
Field.
1 0 1 x All ED/HD
progressive
standards
Pipelined
VSYNC
based
on AV Code V bit
Vertical blanking
interval.
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