Datasheet
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 51 of 107
HD INTERLACE EXTERNAL
HSYNC
AND
VSYNC
CONSIDERATIONS
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01
or higher, the user should set Subaddress 0x02, Bit 1 to high.
To ensure correct timing in HD interlace modes when using
HSYNC
and
VSYNC
synchronization signals. If this bit is set to
low, the first active pixel on each line is masked in HD interlace
modes and the Pr and Pb outputs are swapped when using the
YCrCb 4:2:2 input format. Setting Subaddress 0x02, Bit 1 to low
causes the encoder to behave in the same way as the first
version of silicon (that is, this setting is backward compatible).
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00,
the setting of Subaddress 0x02, Bit 1 has no effect. In this
version of the encoder, the first active pixel is masked and the
Pr and Pb outputs are swapped when using YCrCb 4:2:2 input
format. To avoid these limitations, use the newer revision of
silicon or use a different type of synchronization.
These considerations apply only to the HD interlace modes
with external
HSYNC
and
VSYNC
synchronization (EAV/SAV
mode is not affected and always has correct timing).
There is no negative effect in setting Subaddress 0x02, Bit 0 to
high, and this bit can remain high for all the other video
standards.
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by setting the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this
state, the horizontal and vertical counters remain reset. When
this bit is set back to 0, the internal counters resume counting.
This timing reset applies to the ED/HD timing counters only.
SD SUBCARRIER FREQUENCY LOCK
Subcarrier Frequency Lock (SFL) Mode
In subcarrier frequency lock (SFL) mode (Subaddress 0x84,
Bits[2:1] = 11), the ADV7390/ADV7391/ADV7392/ADV7393
can be used to lock to an external video source. The SFL mode
allows the ADV7390/ADV7391/ADV7392/ADV7393 to
automatically alter the subcarrier frequency to compensate for
line length variations. When the part is connected to a device
such as an ADV7403 video decoder that outputs a digital data
stream in the SFL format, the part automatically changes to the
compensated subcarrier frequency on a line-by-line basis (see
Figure 63). This digital data stream is 67 bits wide, and the
subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock
cycles long.
LLC1
SFL
P19
T
O
P10
ADV7403
VIDEO
DECODER
CLKIN
SFL
PIXE
L PORT
5
RTC
LOW
128
TIME SLOT 01
13 0
14
21
19
F
SC
PL
L INCREMENT
2
VALID
SAMPLE
INVALID
SAMPLE
6768
0
RESET BIT
4
RESER
VED
ADV7390/ADV7391/
ADV7392/ADV7393
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
1
FOR EXAMPLE, VCR OR CABLE.
2
F
SC
PLL
INCREMENT IS 22 BITS LONG. VALUE LOADED INT
O ADV7390/ADV7391/ADV7392/ADV7393 F
SC
DDS REGISTER IS
F
SC
PLL
INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.
3
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4
RESET ADV7390/ADV7391/ADV7392/ADV7393 DDS.
5
REFER TO THE ADV7390/ADV7391
AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXE
L DATA PIN
ASSIGNMENTS.
COMPOSITE
VIDEO
1
H/L TRANSITION
COUNT ST
ART
14 BITS
SUBCARRIER
PHASE
SEQUENCE
BIT
3
DAC 1
DAC 2
DAC 3
4 BITS
RESE
RVED
06234-064
Figure 63. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
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