Datasheet
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 44 of 107
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0xBB Field count Field count x x x Read only 0x0X
Reserved
0
0
0
Reserved
Encoder version code 0 0 Read only; first
encoder version
2
0 1 Read only; second
encoder version
1
x = Logic 0 or Logic 1.
2
See the HD Interlace External
HSYNC
and
VSYNC
Considerations section for information about the first encoder version.
Table 33. Register 0xC9 to Register 0xCE
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0xC9
Teletext control
Teletext enable
0
Disabled.
0x00
1 Enabled.
Teletext request mode 0 Line request signal.
1 Bit request signal.
Teletext input pin
select
1
0
VSYNC
.
1 P0.
Reserved 0 0 0 0 0 Reserved.
0xCA Teletext request
control
Teletext request falling
edge position control
0 0 0 0 0 clock cycles. 0x00
0 0 0 1 One clock cycle.
…
…
…
…
…
1 1 1 0 14 clock cycles.
1 1 1 1 15 clock cycles.
Teletext request rising
edge position control
0 0 0 0 0 clock cycles.
0 0 0 1 One clock cycle.
… … … … …
1 1 1 0 14 clock cycles.
1 1 1 1 15 clock cycles.
0xCB TTX Line Enable 0 Teletext on odd fields 22 21 20 19 18 17 16 15 Setting any of these bits
to 1 enables teletext on
the line number indicated
by the bit settings.
0x00
0xCC TTX Line Enable 1 Teletext on odd fields 14 13 12 11 10 9 8 7 0x00
0xCD TTX Line Enable 2 Teletext on even fields 22 21 20 19 18 17 16 15 0x00
0xCE TTX Line Enable 3 Teletext on even fields 14 13 12 11 10 9 8 7 0x00
1
The use of P0 as the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only.
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