Datasheet
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 41 of 107
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x8B SD Timing Register 1
Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1.
SD
HSYNC
width
0 0 t
a
= one clock cycle. 0x00
0 1 t
a
= four clock cycles.
1 0 t
a
= 16 clock cycles.
1 1 t
a
= 128 clock cycles.
SD
HSYNC
to
VSYNC
delay
0 0 t
b
= 0 clock cycles.
0 1 t
b
= four clock cycles.
1 0 t
b
= eight clock cycles.
1 1 t
b
= 18 clock cycles.
SD
HSYNC
to
VSYNC
rising
edge delay (Mode 1 only)
X
2
0 t
c
= t
b
.
X
2
1 t
c
= t
b
+ 32 µs.
SD
VSYNC
width (Mode 2 only)
0 0 One clock cycle.
0 1 Four clock cycles.
1 0 16 clock cycles.
1 1 128 clock cycles.
SD
HSYNC
to pixel data adjust
0 0 0 clock cycles.
0 1 One clock cycle.
1 0 Two clock cycles.
1 1 Three clock cycles.
0x8C SD F
SC
Register 0
3
Subcarrier Frequency Bits[7:0] x x x x x x x x Subcarrier Frequency
Bits[7:0].
0x1F
0x8D
SD F
SC
Register 1
3
Subcarrier Frequency Bits[15:8] x x x x x x x x Subcarrier Frequency
Bits[15:8].
0x7C
0x8E
SD F
SC
Register 2
3
Subcarrier Frequency Bits[23:16] x x x x x x x x Subcarrier Frequency
Bits[23:16].
0xF0
0x8F
SD F
SC
Register 3
3
Subcarrier Frequency Bits[31:24] x x x x x x x x Subcarrier Frequency
Bits[31:24].
0x21
0x90 SD F
SC
Phase Subcarrier Phase Bits[9:2] x x x x x x x x Subcarrier Phase Bits[9:2]. 0x00
0x91 SD Closed Captioning Extended data on even fields x x x x x x x x Extended Data Bits[7:0]. 0x00
0x92 SD Closed Captioning Extended data on even fields x x x x x x x x Extended Data Bits[15:8]. 0x00
0x93 SD Closed Captioning Data on odd fields x x x x x x x x Data Bits[7:0]. 0x00
0x94
SD Closed Captioning
Data on odd fields
x
x
x
x
x
x
x
x
Data Bits[15:8].
0x00
0x95
SD Pedestal Register 0
Pedestal on odd fields
17
16
15
14
13
12
11
10
Setting any of these bits
to 1 disables the
pedestal on the line
number indicated by
the bit settings.
0x00
0x96 SD Pedestal Register 1 Pedestal on odd fields 25 24 23 22 21 20 19 18 0x00
0x97 SD Pedestal Register 2 Pedestal on even fields 17 16 15 14 13 12 11 10 0x00
0x98 SD Pedestal Register 3 Pedestal on even fields 25 24 23 22 21 20 19 18 0x00
1
x = Logic 0 or Logic 1.
2
X = don’t care.
3
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
Table 31. Register 0x99 to Register 0xA5
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x99 SD CGMS/WSS 0 SD CGMS data x x x x CGMS Data Bits[C19:C16] 0x00
SD CGMS CRC
0
Disabled
1 Enabled
SD CGMS on odd fields 0 Disabled
1 Enabled
SD CGMS on even fields 0 Disabled
1
Enabled
SD WSS 0 Disabled
1 Enabled
0x9A SD CGMS/WSS 1 SD CGMS/WSS data x x x x x x CGMS Data Bits[C13:C8] or
WSS Data Bits[W13:W8]
0x00
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