Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 39 of 107
Table 28. Register 0x84 to Register 0x87
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x84
SD Mode
Register 4
Reserved
0
0x00
SD SFL/SCR/TR mode select 0 0 Disabled.
1 1 SFL mode enabled.
SD active video length 0 720 pixels.
1 710 (NTSC), 702 (PAL).
SD chroma 0 Chroma enabled.
1 Chroma disabled.
SD burst 0 Enabled.
1 Disabled.
SD color bars
0
Disabled.
1 Enabled.
SD luma/chroma swap 0 DAC 2 = luma, DAC 3 = chroma.
1
DAC 2 = chroma, DAC 3 = luma.
0x86 SD Mode
Register 5
NTSC color subcarrier adjust (delay from
the falling edge of output
HSYNC
pulse to
the start of color burst)
0 0 5.17 μs. 0x02
0 1 5.31 μs.
1 0 5.59 μs (must be set for
Macrovision compliance).
1
1
Reserved.
Reserved 0
SD EIA/CEA-861B synchronization
compliance
0 Disabled.
1 Enabled.
Reserved 0 0
SD horizontal/vertical counter mode
1
0 Update field/line counter.
1 Field/line counter free running.
SD RGB color swap
2
0 Normal.
1 Color reversal enabled.
0x87 SD Mode
Register 6
SD luma and color scale control 0 Disabled. 0x00
1 Enabled.
SD luma scale saturation 0 Disabled.
1 Enabled.
SD hue adjust
0
Disabled.
1 Enabled.
SD brightness 0 Disabled.
1 Enabled.
SD luma SSAF gain 0 Disabled.
1
Enabled.
SD input standard autodetection 0 Disabled.
1 Enabled.
Reserved 0 0 must be written to this bit.
SD RGB input enable
2
0 SD YCrCb input.
1 SD RGB input.
1
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
2
Available on the ADV7392/ADV7393 (40-pin devices) only.
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