Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 34 of 107
Table 23. Register 0x39 to Register 0x43
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x39 ED/HD Mode
Register 7
Reserved 0 0 0 0 0 0x00
ED/HD EIA/CEA-861B
synchronization compliance
0 Disabled
1 Enabled
Reserved 0 0
0X3A ED/HD Mode
Register 8
INV_PHSYNC_POL 0 Disabled 0x00
1 Enabled
INV_PVSYNC_POL 0 Disabled
1 Enabled
INV_PBLANK_POL
0
Disabled
1 Enabled
Reserved 0 0 0 0 0
0x40 ED/HD
sharpness filter
gain
ED/HD sharpness filter gain
Value A
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
…
…
…
…
…
0 1 1 1 Gain A = +7
1 0 0 0 Gain A = −8
… … … … …
1 1 1 Gain A = −1
ED/HD sharpness filter gain
Value B
0 0 0 0 Gain B = 0
0 0 0 1 Gain B = +1
… … … … …
0 1 1 1 Gain B = +7
1
0
0
0
Gain B = −8
… … … … …
1 1 1 1 Gain B = −1
0x41 ED/HD CGMS
Data 0
ED/HD CGMS data bits 0 0 0 0 C19 C18 C17 C16 CGMS C19 to C1
6
0x00
0x42 ED/HD CGMS
Data 1
ED/HD CGMS data bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS C15 to C8 0x00
0x43 ED/HD CGMS
Data 2
ED/HD CGMS data bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS C7 to C0 0x00
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