Datasheet
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 33 of 107
Table 22. Register 0x34 to Register 0x38
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x34 ED/HD Mode
Register 5
ED/HD timing reset 0 Internal ED/HD timing counters enabled. 0x48
1 Resets the internal ED/HD timing counters.
ED/HD
HSYNC
control
2
0
HSYNC
output control (see Table 55).
1
ED/HD
VSYNC
control
2
0
VSYNC
output control (see Table 56).
1
Reserved 1
ED Macrovision® enable
3
0 ED Macrovision disabled.
1 ED Macrovision enabled.
Reserved
0
0 must be written to this bit.
ED/HD
VSYNC
input/field
input
0 0 = Field input.
1
1 =
VSYNC
input.
ED/HD horizontal/vertical
counter mode
4
0 Update field/line counter.
1 Field/line counter free running.
0x35 ED/HD Mode
Register 6
Reserved 0 0x00
Reserved
0
ED/HD sync on PrPb 0 Disabled.
1 Enabled.
ED/HD color DAC swap 0 DAC 2 = Pb, DAC 3 = Pr.
1 DAC 2 = Pr, DAC 3 = Pb.
ED/HD gamma correction
curve select
0 Gamma Correction Curve A.
1 Gamma Correction Curve B.
ED/HD gamma correction
enable
0 Disabled.
1 Enabled.
ED/HD adaptive filter
mode
0
Mode A.
1 Mode B.
ED/HD adaptive filter
enable
0 Disabled.
1
Enabled.
0x36 ED/HD Y level
5
ED/HD Test Pattern Y level x x x x x x x x Y level value. 0xA0
0x37 ED/HD Cr level
5
ED/HD Test Pattern Cr level x x x x x x x x Cr level value. 0x80
0x38 ED/HD Cb level
5
ED/HD Test Pattern Cb level x x x x x x x x Cb level value. 0x80
1
x = Logic 0 or Logic 1.
2
Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
3
Applies to the ADV7390 and ADV7392 only.
4
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
5
For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
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