Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 31 of 107
Table 20. Register 0x30
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Note Value
0x30 ED/HD Mode
Register 1
ED/HD output standard 0 0 EIA-770.2 output
EIA-770.3 output
ED
HD
0x00
0 1 EIA-770.1 output
1 0 Output levels for full
input range
1 1 Reserved
ED/HD input
synchronization format
0 External
HSYNC
,
VSYNC
and field inputs
1
1 Embedded EAV/SAV
codes
ED/HD standard
2
0
0
0
0
0
SMPTE 293M, ITU-BT.1358
525p at 59.94 Hz
0 0 0 1 0 BTA-1004, ITU-BT.1362 525p at 59.94 Hz
0 0 0 1 1 ITU-BT.1358 625p at 50 Hz
0 0 1 0 0 ITU-BT.1362 625p at 50 Hz
0 0 1 0 1 SMPTE 296M-1,
SMPTE 274M-2
720p at
60 Hz/59.94 Hz
0 0 1 1 0 SMPTE 296M-3 720p at 50 Hz
0 0 1 1 1 SMPTE 296M-4,
SMPTE 274M-5
720p at
30 Hz/29.97 Hz
0 1 0 0 0 SMPTE 296M-6 720p at 25 Hz
0
1
0
0
1
SMPTE 296M-7,
SMPTE 296M-8
720p at
24 Hz/23.98 Hz
0 1 0 1 0 SMPTE 240M 1035i at
60 Hz/59.94 Hz
0 1 0 1 1 Reserved
0 1 1 0 0 Reserved
0 1 1 0 1 SMPTE 274M-4,
SMPTE 274M-5
1080i at
30 Hz/29.97 Hz
0 1 1 1 0 SMPTE 274M-6 1080i at 25 Hz
0 1 1 1 1 SMPTE 274M-7,
SMPTE 274M-8
1080p at
30 Hz/29.97 Hz
1 0 0 0 0 SMPTE 274M-9 1080p at 25 Hz
1 0 0 0 1 SMPTE 274M-10,
SMPTE 274M-11
1080p at
24 Hz/23.98 Hz
1 0 0 1 0 ITU-R BT.709-5 1080Psf at 24 Hz
10011 to 11111 Reserved
1
Synchronization can be controlled with a combination of either
HSYNC
and
VSYNC
inputs or
HSYNC
and field inputs, depending on Subaddress 0x34, Bit 6.
2
See the HD Interlace External
HSYNC
and
VSYNC
Considerations section for more information.
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