Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 30 of 107
Table 19. Register 0x0B to Register 0x17
SR7 to Bit Number
1
Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x0B DAC 1, DAC 2,
DAC 3 output
levels
Positive gain to DAC output voltage 0 0 0 0 0 0 0 0 0%. 0x00
0 0 0 0 0 0 0 1 +0.018%.
0 0 0 0 0 0 1 0 +0.036%.
… … … … … … … … …
0 0 1 1 1 1 1 1 +7.382%.
0 1 0 0 0 0 0 0 +7.5%.
Negative gain to DAC output voltage 1 1 0 0 0 0 0 0 −7.5%.
1 1 0 0 0 0 0 1 −7.382%.
1 0 0 0 0 0 1 0 −7.364%.
… … … … … … … … …
1 1 1 1 1 1 1 1 −0.018%.
0x0D DAC power
mode
DAC 1 low power mode 0 DAC 1 low power
disabled.
0x00
1
DAC 1 low power enabled.
DAC 2 low power mode 0 DAC 2 low power
disabled.
1 DAC 2 low power enabled.
DAC 3 low power mode 0 DAC 3 low power
disabled.
1 DAC 3 low power enabled.
SD/ED oversample rate select 0 SD = 16×, ED = 8×.
1 SD = 8×, ED = 4×.
Reserved 0 0 0 0
0x10 Cable detection DAC 1 cable detect 0 Cable detected on
DAC 1.
0x00
Read only 1 DAC 1 unconnected.
DAC 2 cable detect
0
Cable detected on
DAC 2.
Read only 1 DAC 2 unconnected.
Reserved 0 0
Unconnected DAC autopower-down
0
DAC autopower-down
disable.
1 DAC autopower-down
enable.
Reserved 0 0 0
0x13 Pixel Port
Readback A
2
P[7:0] readback (ADV7390/ADV7391) x x x x x x x x Read only. 0xXX
P[15:8] readback (ADV7392/ADV7393)
0x14 Pixel Port
Readback B
2
P[7:0] readback (ADV7392/ADV7393) x x x x x x x x Read only. 0xXX
0x16 Control port
readback
2
Reserved x x x Read only. 0xXX
VSYNC
readback
x
HSYNC
readback
x
SFL readback x
Reserved x x
0x17
Software reset
Reserved
0
0x00
Software reset 0 Writing a 1 resets the
device; this is a self-
clearing bit.
1
Reserved. 0 0 0 0 0 0
1
x = Logic 0 or Logic 1.
2
For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.
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