Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 26 of 107
MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the
ADV7390/ADV7391/ADV7392/ADV7393 through a 2-wire
serial (I
2
C-compatible) bus. After power-up or reset, the MPU
port is configured for I
2
C operation.
I
2
C OPERATION
The ADV7390/ADV7391/ADV7392/ADV7393 support a 2-wire
serial (I
2
C-compatible) microprocessor bus driving multiple
peripherals. This port operates in an open-drain configuration.
Two wires, serial data (SDA) and serial clock (SCL), carry
information between any device connected to the bus and the
ADV7390/ADV7391/ADV7392/ADV7393. The slave address
depends on the device (ADV7390, ADV7391, ADV7392, or
ADV7393), the operation (read or write), and the state of the
ALSB pin (0 or 1). See Table 16, Figure 47, and Figure 48. The
LSB sets either a read or a write operation. Logic 1 corresponds
to a read operation, and Logic 0 corresponds to a write operation.
A1 is controlled by setting the ALSB pin of the ADV7390/
ADV7391/ADV7392/ADV7393 to Logic 0 or Logic 1.
Table 16. ADV7390/ADV7391/ADV7392/ADV7393 I
2
C
Slave Addresses
Device ALSB Operation Slave Address
ADV7390
and
ADV7392
0 Write 0xD4
0 Read 0xD5
1 Write 0xD6
1
Read
0xD7
ADV7391
and
ADV7393
0 Write 0x54
0 Read 0x55
1 Write 0x56
1 Read 0x57
1 1
0
1
0 1 A1 X
READ/WRITE
CONTROL
0 WRITE
1 READ
06234-045
ADDRESS
CONTROL
SET UP BY
ALSB
Figure 47. ADV7390/ADV7392 I
2
C Slave Address
0 1 0 1 0
1 A1 X
READ/WRITE
CONTROL
0 WRITE
1 READ
06234-046
ADDRESS
CONTROL
SET UP BY
ALSB
Figure 48. ADV7391/ADV7393 I
2
C Slave Address
The various devices on the bus use the following protocol. The
master initiates a data transfer by establishing a start condition,
defined by a high-to-low transition on SDA while SCL remains
high. This indicates that an address/data stream follows. All
peripherals respond to the start condition and shift the next
eight bits (7-bit address plus the R/
W
bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
occurs when the device monitors the SDA and SCL lines waiting
for the start condition and the correct transmitted address. The
R/
W
bit determines the direction of the data.
Logic 0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first byte
means that the master reads information from the peripheral.
The ADV7390/ADV7391/ADV7392/ADV7393 act as a standard
slave device on the bus. The data on the SDA pin is eight bits
long, supporting the 7-bit addresses plus the R/
W
bit. It interprets
the first byte as the device address and the second byte as the
starting subaddress. There is a subaddress auto-increment
facility. This allows data to be written to or read from registers
in ascending subaddress sequence starting at any valid subaddress.
A data transfer is always terminated by a stop condition. The
user can also access any unique subaddress register on a one-
by-one basis without updating all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should issue only a start condition, a stop condition, or a
stop condition followed by a start condition. If an invalid
subaddress is issued by the user, the ADV7390/ADV7391/
ADV7392/ADV7393 do not issue an acknowledge but returns
to the idle condition. If the user uses the auto-increment method
of addressing the encoder and exceeds the highest subaddress,
the following actions are taken:
• In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge condition
occurs when the SDA line is not pulled low on the ninth pulse.
• In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7390/ADV7391/ADV7392/ADV7393, and the
part returns to the idle condition.
Figure 49 shows an example of data transfer for a write sequence
and the start and stop conditions. Figure 50 shows bus write
and read sequences.
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