Datasheet
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 19 of 107
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
V
DD_IO
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
2P2
3
P3
4
P4
5
V
DD
6DGND
7
P5
8P6
24
R
SET
23
COM
P
22
DAC 1
21 DAC 2
20 DAC 3
19
V
AA
18 AGND
17 PV
DD
9P7
10ALSB
11SDA
12SCL
13CLKIN
14
RESET
15PGND
16EXT_LF
32
GND_IO
31
P1
30
P0
29
DGND
28
V
DD
27
HSYNC
26
VSYNC
25
SFL
T
OP
VIEW
(Not to Scale)
ADV7390/
ADV7391
06234-017
Figure 18. ADV7390/ADV7391 Pin Configuration
V
DD_IO
P4
P5
P6
P7
V
DD
DGND
P8
P9
P10
PV
DD
AGND
V
AA
DAC 3
DAC 2
DAC 1
COMP
R
SET
EXT_LF
PGND
P0
V
DD
DGND
P1
P2
P3
GND_IO
SFL
HSYNC
VSYNC
P11
ALSB
SDA
P12
P14
P13
P15
CLKIN
RESET
SCL
06234-018
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
ADV7392/
ADV7393
TOP VIEW
(Not to Scale)
Figure 19. ADV7392/ADV7393 Pin Configuration
06234-147
1
A
B
C
D
E
F
2 3
4
V
DD
P0
V
DD_IO
R
SET
DAC1
HSYNC
VSYNC
SFL P1
P2
V
AA
COMP DGND P3 P4
AGND
GND_IO
RESET V
DD
DGND
PV
DD
EXT_LF
ALSB P5 P6
PGND SDA SCL CLKIN P7
5
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
BALL A1 CORNER
Figure 20. ADV7390BCBZ-A Pin Configuration
Table 15. Pin Function Descriptions
Pin No.
1
Mnemonic
Input/
Output Description
ADV7390/
ADV7391
ADV7392/
ADV7393
ADV7390
WLCSP
9 to 7, 4 to 2,
31, 30
N/A F5, E5, E4, C5,
C4, B5, B4, A4
P7 to P0 I 8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for
input modes (ADV7390/ADV7391).
N/A 18 to 15, 11 to
8, 5 to 2, 39 to
37, 34
N/A P15 to P0 I 16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for
input modes (ADV7392/ADV7393).
13 19 F4 CLKIN I Pixel Clock Input for HD (74.25 MHz), ED
2
(27 MHz or 54 MHz),
or SD (27 MHz).
27 33 A2
HSYNC
I/O Horizontal Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD horizontal
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
26 32 B2
VSYNC
I/O Vertical Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
25 31 B3 SFL I/O Subcarrier Frequency Lock (SFL) Input.
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