Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 17 of 107
Cb
Y
Cr Y
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
PIXEL PORT
VSYNC
HSYNC
06234-014
Figure 16. SD Input Timing Diagram (Timing Mode 1)
t
3
t
3
t
4
t
7
t
8
t
5
SDA
SCL
t
1
t
2
t
6
06234-015
Figure 17. MPU Port Timing Diagram (I
2
C Mode)
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