Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 16 of 107
Y0 Y1
Y2 Y3
a
Cr2Cb2Cr0Cb0
b
Y OUTPUT
HSYNC
VSYNC
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
PIXEL PORT
06234-012
Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
PIXEL PORT
Cb0 Y0
Cr0 Y1
a
HSYNC
VSYNC
b
Y OUTPUT
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
06234-013
Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
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