Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. J | Page 15 of 107
Y0 Y1
Y2 Y3
a
Cr2Cb2Cr0Cb0
b
Y OUTPUT
HSYNC
VSYNC
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
PIXEL PORT*
06234-010
Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
Cb0
Y0
Cr0 Y1
a
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
HSYNC
VSYNC
b
Y OUTPUT
PIXEL PORT
06234-011
Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (
HSYNC
/
VSYNC
) Input Timing Diagram
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