Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 12 of 107
TIMING DIAGRAMS
The following abbreviations are used in Figure 4 to Figure 11:
• t
9
= clock high time
• t
10
= clock low time
• t
11
= data setup time
• t
12
= data hold time
• t
13
= control output access time
• t
14
= control output hold time
In addition, see Table 35 for the ADV7390/ADV7391 pixel port
input configuration and Table 36 for the ADV7392/ADV7393
pixel port input configuration.
t
9
CLKIN
t
10
CONTRO
L
OUTPUTS
HSYNC
VSYNC
Cr2
Cb2Cr0
Cb0
IN MASTER/SL
AVE MODE
IN SL
A
VE MODE
Y0 Y1
Y2
PIXE
L
PORT
CONTRO
L
INPUTS
t
12
t
11
t
13
t
14
06234-002
Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000
IN MASTER/SLAVE MODE
IN SLAVE MODE
CLKIN
CONTROL
OUTPUTS
t
9
t
10
Cr2
Cb2
Cr0Cb0
Y0 Y1
Y2
Y3
t
12
t
14
t
11
t
13
HSYNC
VSYNC
CONTROL
INPUTS
PIXEL PORT
PIXEL PORT
06234-003
Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000
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