Datasheet
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. J | Page 100 of 107
Table 105. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 106. 16-Bit 625p YCrCb In, RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x10 ED-SDR input mode.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x18
625p at 50 Hz. HSYNC
/VSYNC synch-
ronization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 107. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 108. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
0x33 0x6C 10-bit input enabled.
Table 109. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 110. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10
RGB output enabled. RGB output sync
enabled.
0x30 0x04
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
0x33 0x6C 10-bit input enabled.
Table 111. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 112. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30 0x1C
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
0x33 0x6C 10-bit input enabled.
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