User manual

READY pin and manage the transaction mode.

5.1.4. SPI Operation

The SPI operation includes four parameters: SPI port configuration, speed and

timing, access, and modification.

SPI port configuration

The SPI port must be configured in the 0 mode (refer to section 5.1.1 on page 37)

to communicate with the receiver module. To prevent the receiver module to go into

the bootloader mode, the port must never have all SPI input pins (nCS, MOSI and

CLK) set to the low level for more than 100 milliseconds at power up or when

performing a hard reset.

Speed and timing

For the read operation, a delay is needed between the header (group containing the

opcode, address, and size data), and the return data stream to let the receiver

module to decode the request and get the ready data to the clock. This delay can be

set to 1 millisecond. During this delay, the SPI clock must be halted and the nCS

must be staying asserted (see Figure 20 on page 40).

The SPI clock frequency can be in the range between 500 kHz and 25 MHz.

Access

In order to access a parameter, you need to add a parameter offset to the

associated bank start base address. Use the parameter length to get or set the

whole parameter field.

Modification

To modify a parameter:

1. Disable the write protection of the module by sending the write enabled

command.

2. Poll the status register to get the ready state and write enabled flag

asserted.

3. Send the new parameter value.

4. Poll the status register to get the ready state.