User manual

40 P/N 54A0028-2 012017© 2017 LeddarTech Inc. Printed in Canada. All rights reserved.
The status register and bit flags are presented in Table 16.
Table 16: Status register
Bit
Name
Access
Description
7:2
Reserved
R/W
Future use
1
Write enable
latch
R
0 = Write disabled
1 = Write enabled
0
Module
ready
R
0 = Module ready
1 = Module busy (programming, erasing)
Data chronograms are represented in Figure 20 and Figure 21, and opcode and
register chronograms are presented in Figure 22 and Figure 23.
Figure 20: Read data chronogram
Figure 21: Write data chronogram
Figure 22: Single opcode chronogram (write enabled example)
Figure 23: Read status register chronogram