User manual

38 P/N 54A0028-2 012017© 2017 LeddarTech Inc. Printed in Canada. All rights reserved.
Table 13: Basic modes
Mode
Clock Polarity
CPOL
Clock Phase
CPHA
0
0
0
1
0
1
2
1
0
3
1
1
5.1.2. SPI Protocol
The universal SPI protocol uses a combination of standard commands for FLASH and
SRAM memories.
Each SPI packet contains a header, a payload, and a cyclic redundancy check (CRC).
The first byte of the header corresponds to an instruction opcode. It is followed by a
24-bit address and the 16-bit size of the payload. The payload contains a number of
user-data bytes. The last 16 bits of the packet is the CRC16 (IBM) of both header
and payload. The table below summarizes the structure of an SPI packet. It is noted
that address and the CRC are packed with the most significant byte first while the
first byte of data corresponds to the least significant byte.
Table 14: Byte offsets
Field
Opcode
Address
Size
Data
CRC16
Byte
offset
1
2
3
4
5
6
7
…
7 + n
8 + n
9 + n
The supported opcodes are presented in Table 15.