User manual

Operator's Manual
919586 RevA
139
Name
Purpose
SR-RISE-700-930-MIN-CLKp
SR-RISE-700-930-MIN-CLKn
Official MIPI D-PHY Test Algorithms
Specific test information is maintained by the MIPI Alliance and can be found at www.mipi.org.
Note: Registration with the Alliance is required to access the document.
HS (HIGH SPEED) TESTS
All Dphy1 - X dialogs have controls for On, Category, Measure On, Measure, Burst Index, and Actions for Dphy1
buttons. When the HS Rise & Fall category is selected, DATA/CLK-VOD1, DATA/CLK-VOD0, and Find Levels
controls are also shown.
With HS (High Speed) selected as your Mode on the Mode and Input Selection Area of the MIPI D-PHY Dialog
(on page 135), Categories and Measurements on the Dphy1 - X dialogs vary in the following manner.
Note: For LP (Low Power) Tests, refer to the LP (Low Power) Tests (on page 136) topic.
Category and Measure Combinations for HS Dphy1 - X Dialogs
BRIEF HS CLOCK TO DATA TIMING TEST DESCRIPTIONS
 With HS Clock To Data Timing selected in the Category field, the following Measure values are available:
FirstBit, TCLK-PRE, TCLK-POST, TSETUP, and THOLD.
Name
Purpose
FirstBit
To verify that the DUT HS Clock is properly aligned to the payload data signaling.
TCLK-PRE
To verify that the time that the HS clock is driven prior to an associated Data Lane beginning the
transition from LP to HS mode (TCLK-PRE), is greater than the minimum required value.
TCLK-POST
To verify that the DUT Clock Lane HS transmitter continues to transmit clock signaling for the
minimum required duration (TCLK-POST) after the last Data Lane switches to LP mode.
TSETUP
To verify the Setup time between the clock and data signaling is within conformance limits.
THOLD
To verify the Hold time between the clock and data signaling is within conformance limits.
BRIEF HS DATA TIMING TEST DESCRIPTIONS
 With HS Data Timing selected in the Category field, the following Measure values are available:
TLP-01, THS-PREPARE, THS-ZERO, THS-PREPARE+ZERO, THS-SYNC, THS-TRAIL, TEOT, TREOT, and THS-
EXIT.