User's Manual
Table Of Contents
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- 2. Typical Applications
- 3. Feature
- 4. Pin Configurations
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- I/O
- Function Description
- O
- Connected to a bypass capacitor for RSSI.
- O
- Connected to a bypass capacitor for internal Regulator bias point.
- I
- LNA input. Connected to matching circuit.
- O
- PA input. Connected to matching circuit.
- I
- RF Choke input. Connected to matching circuit.
- I
- VCO supply voltage input.
- O
- Charge-pump. Connected to loop filter.
- I
- PLL supply voltage input.
- I
- Crystal oscillator input.
- O
- Crystal oscillator output.
- I
- SPI chip select.
- I
- SPI clock input pin.
- I
- Connected to a bypass capacitor to supply voltage for digital part.
- I/O
- SPI read/write data.
- G
- Ground
- I/O
- I/O
- O
- I
- Regulator input (External Power Input)
- O
- G
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 6. Chip Block Diagram
- 7. Absolute Maximum Ratings
- 8. Electrical Specification
- 9. Control Register
- 9.1 Control register table
- 9.2 Control register description
- 9.2.1 Mode Register (Address: 00h)
- 9.2.2 Mode Control Register (Address: 01h)
- 9.2.3 Calibration Control Register (Address: 02h)
- 9.2.4 FIFO Register I (Address: 03h)
- 9.2.5 FIFO Register II (Address: 04h)
- 9.2.6 FIFO DATA Register (Address: 05h)
- 9.2.7 ID DATA Register (Address: 06h)
- 9.2.8 RC OSC Register I (Address: 07h)
- 9.2.9 RC OSC Register II (Address: 08h)
- 9.2.10 RC OSC Register III (Address: 09h)
- 9.2.11 CKO Pin Control Register (Address: 0Ah)
- 9.2.12 GIO1 Pin Control Register I (Address: 0Bh)
- 9.2.13 GIO2 Pin Control Register II (Address: 0Ch)
- 9.2.14 Clock Register (Address: 0Dh)
- 9.2.15 PLL Register I (Address: 0Eh)
- 9.2.16 PLL Register II (Address: 0Fh)
- 9.2.17 PLL Register III (Address: 10h)
- 9.2.18 PLL Register IV (Address: 11h)
- 9.2.19 PLL Register V (Address: 12h)
- 9.2.20 Channel Group Register I (Address: 13h)
- 9.2.21 Channel Group Register II (Address: 14h)
- 9.2.22 TX Register I (Address: 15h)
- 9.2.23 TX Register II (Address: 16h)
- 9.2.24 Delay Register I (Address: 17h)
- 9.2.25 Delay Register II (Address: 18h)
- 9.2.26 RX Register (Address: 19h)
- 9.2.27 RX Gain Register I (Address: 1Ah)
- 9.2.28 RX Gain Register II (Address: 1Bh)
- 9.2.29 RX Gain Register III (Address: 1Ch)
- 9.2.30 RX Gain Register IV (Address: 1Dh)
- 9.2.31 RSSI Threshold Register (Address: 1Eh)
- 9.2.32 ADC Control Register (Address: 1Fh)
- 9.2.33 Code Register I (Address: 20h)
- 9.2.34 Code Register II (Address: 21h)
- 9.2.35 Code Register III (Address: 22h)
- 9.2.36 IF Calibration Register I (Address: 23h)
- 9.2.37 IF Calibration Register II (Address: 24h)
- 9.2.38 VCO current Calibration Register (Address: 25h)
- 9.2.39 VCO band Calibration Register I (Address: 26h)
- 9.2.40 VCO band Calibration Register II (Address: 27h)
- 9.2.41 VCO Deviation Calibration Register I (Address: 28h)
- 9.2.42 VCO Deviation Calibration Register II (Address: 29h)
- 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0)
- 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1)
- 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2)
- 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3)
- 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4)
- 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5)
- 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6)
- 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7)
- 9.2.44 VCO Modulation Delay Register (Address: 2Bh)
- 9.2.45 Battery detect Register (Address: 2Ch)
- 9.2.46 TX test Register (Address: 2Dh)
- 9.2.47 Rx DEM test Register I (Address: 2Eh)
- 9.2.48 Rx DEM test Register II (Address: 2Fh)
- 9.2.49 Charge Pump Current Register I (Address: 30h)
- 9.2.50 Charge Pump Current Register II (Address: 31h)
- 9.2.51 Crystal test Register (Address: 32h)
- 9.2.52 PLL test Register (Address:33h)
- 9.2.53 VCO test Register I (Address:34h)
- 9.2.54 RF Analog Test Register (Address: 35h)
- 9.2.55 AES Key data Register (Address: 36h)
- 9.2.56 Channel Select Register (Address: 37h)
- 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0)
- 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1)
- 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2)
- 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3)
- 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4)
- 9.2.58 Data Rate Clock Register (Address: 39h)
- 9.2.59 FCR Register (Address: 3Ah)
- 9.2.60 ARD Register (Address: 3Bh)
- 9.2.61 AFEP Register (Address: 3Ch)
- 9.2.62 FCB Register (Address: 3Dh)
- 9.2.63 KEYC Register (Address: 3Eh)
- 9.2.64 USID Register (Address: 3Fh)
- 10. SPI
- 10.1 SPI Format
- 10.2 SPI Timing Characteristic
- 10.3 SPI Timing Chart
- 10.4 Strobe Commands
- 10.4.1 Strobe Command - Sleep Mode
- 10.4.2 Strobe Command - ldle Mode
- 10.4.3 Strobe Command - Standby Mode
- 10.4.4 Strobe Command - PLL Mode
- 10.4.5 Strobe Command - RX Mode
- 10.4.6 Strobe Command - TX Mode
- ÿþ1 0 . 4 . 7 S t r o b e C o m m a n d F I F O W r i t e P o i n t e r R e s e t
- ÿþ1 0 . 4 . 8 S t r o b e C o m m a n d F I F O R e a d P o i n t e r R e s e t
- ÿþ1 0 . 4 . 9 S t r o b e C o m m a n d D e e p S l e e p M o d e
- 10.5 Reset Command
- 10.6 ID Accessing Command
- 10.7 FIFO Accessing Command
- 11. State machine
- 12. Crystal Oscillator
- 13. System Clock
- 14. Transceiver LO Frequency
- 15. Calibration
- 16. FIFO (First In First Out)
- 17. ADC (Analog to Digital Converter)
- 18. Battery Detect
- 19. Auto-ack and auto-resend
- 20. RC Oscillator
- 21. AES128 Security Packet
- 22. Application circuit
- 23. Abbreviations
- 24. Ordering Information
- 25. Package Information
- 26. Top Marking Information
- 27. Reflow Profile
- 28. Tape Reel Information
- 29. Product Status
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- 新建 Microsoft Word 文档 _3_
LBA7130
Oct., 2012, Version 0.6 (PRELIMINARY) 81 AMICCOM Electronics Corporation
22. Application circuit
22.1 MD70-A01
AMICCOM’s ref. design module, MD7130-A01, max 5 dBm output power, application circuit example.
C1
470pF
SCS
C2
100pF
C5
100pF
VDD_A
C6
0.1uF
R1
NC
SCK
C9
NC
SDIO
C8
2.2nF
G I O1
C KO
G I O2
G ND
G ND
VIN
G ND
C10
0.1uF
1
2
3
4
5
6
7
8
9
10
J1
CON/10P 2.0
1
2
J2
CON/2P 2.0
C12
NC
1
2
J3
CON/2P 2.0
C13
NC
C7
2.2uF
SDIO
SCK
SCS
VDD_A
TP1
ANTENNA
CKO
GIO2
GIO1
V IN
C15
1.8pF
A NT
C4 2.2uF
L2
2.7nH
C3
4.7uF
VDD_A
C11
100pF
1
3
G ND
2
G ND
4
Y2 NC
1
3
G ND
2
G ND
4
Y3
16M Hz XTA L_ 3. 2*2. 5
Y1 NC
BP_RSSI
1
BP_BG
2
RFI
3
RFC
5
RFO
4
V DD _ VC O
6
CP
7
VDD_PLL
8
XI
9
XO
10
G ND
15
SCS
11
SCK
12
SDIO
14
VDD_D
13
CKO
18
GIO2
17
GIO1
16
REGI
19
VDD_A
20
A7130PKG
U1
A7130
Remark
1. RF Matching to 50Ω.
2. RX and TX signal are combined internally to RFI pin only so that
RFSP bit = 0 (DASP0 register = 0x34).
3. Recommend 16MHz crystal with 18 pF Cload.
4. Recommend to let C12 and C13 NC because of enabling on-chip Xtal Capacitors by (INTXC = 1 and CSXTAL = [10100]).