User's Manual
Table Of Contents
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- 2. Typical Applications
- 3. Feature
- 4. Pin Configurations
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- I/O
- Function Description
- O
- Connected to a bypass capacitor for RSSI.
- O
- Connected to a bypass capacitor for internal Regulator bias point.
- I
- LNA input. Connected to matching circuit.
- O
- PA input. Connected to matching circuit.
- I
- RF Choke input. Connected to matching circuit.
- I
- VCO supply voltage input.
- O
- Charge-pump. Connected to loop filter.
- I
- PLL supply voltage input.
- I
- Crystal oscillator input.
- O
- Crystal oscillator output.
- I
- SPI chip select.
- I
- SPI clock input pin.
- I
- Connected to a bypass capacitor to supply voltage for digital part.
- I/O
- SPI read/write data.
- G
- Ground
- I/O
- I/O
- O
- I
- Regulator input (External Power Input)
- O
- G
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 6. Chip Block Diagram
- 7. Absolute Maximum Ratings
- 8. Electrical Specification
- 9. Control Register
- 9.1 Control register table
- 9.2 Control register description
- 9.2.1 Mode Register (Address: 00h)
- 9.2.2 Mode Control Register (Address: 01h)
- 9.2.3 Calibration Control Register (Address: 02h)
- 9.2.4 FIFO Register I (Address: 03h)
- 9.2.5 FIFO Register II (Address: 04h)
- 9.2.6 FIFO DATA Register (Address: 05h)
- 9.2.7 ID DATA Register (Address: 06h)
- 9.2.8 RC OSC Register I (Address: 07h)
- 9.2.9 RC OSC Register II (Address: 08h)
- 9.2.10 RC OSC Register III (Address: 09h)
- 9.2.11 CKO Pin Control Register (Address: 0Ah)
- 9.2.12 GIO1 Pin Control Register I (Address: 0Bh)
- 9.2.13 GIO2 Pin Control Register II (Address: 0Ch)
- 9.2.14 Clock Register (Address: 0Dh)
- 9.2.15 PLL Register I (Address: 0Eh)
- 9.2.16 PLL Register II (Address: 0Fh)
- 9.2.17 PLL Register III (Address: 10h)
- 9.2.18 PLL Register IV (Address: 11h)
- 9.2.19 PLL Register V (Address: 12h)
- 9.2.20 Channel Group Register I (Address: 13h)
- 9.2.21 Channel Group Register II (Address: 14h)
- 9.2.22 TX Register I (Address: 15h)
- 9.2.23 TX Register II (Address: 16h)
- 9.2.24 Delay Register I (Address: 17h)
- 9.2.25 Delay Register II (Address: 18h)
- 9.2.26 RX Register (Address: 19h)
- 9.2.27 RX Gain Register I (Address: 1Ah)
- 9.2.28 RX Gain Register II (Address: 1Bh)
- 9.2.29 RX Gain Register III (Address: 1Ch)
- 9.2.30 RX Gain Register IV (Address: 1Dh)
- 9.2.31 RSSI Threshold Register (Address: 1Eh)
- 9.2.32 ADC Control Register (Address: 1Fh)
- 9.2.33 Code Register I (Address: 20h)
- 9.2.34 Code Register II (Address: 21h)
- 9.2.35 Code Register III (Address: 22h)
- 9.2.36 IF Calibration Register I (Address: 23h)
- 9.2.37 IF Calibration Register II (Address: 24h)
- 9.2.38 VCO current Calibration Register (Address: 25h)
- 9.2.39 VCO band Calibration Register I (Address: 26h)
- 9.2.40 VCO band Calibration Register II (Address: 27h)
- 9.2.41 VCO Deviation Calibration Register I (Address: 28h)
- 9.2.42 VCO Deviation Calibration Register II (Address: 29h)
- 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0)
- 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1)
- 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2)
- 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3)
- 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4)
- 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5)
- 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6)
- 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7)
- 9.2.44 VCO Modulation Delay Register (Address: 2Bh)
- 9.2.45 Battery detect Register (Address: 2Ch)
- 9.2.46 TX test Register (Address: 2Dh)
- 9.2.47 Rx DEM test Register I (Address: 2Eh)
- 9.2.48 Rx DEM test Register II (Address: 2Fh)
- 9.2.49 Charge Pump Current Register I (Address: 30h)
- 9.2.50 Charge Pump Current Register II (Address: 31h)
- 9.2.51 Crystal test Register (Address: 32h)
- 9.2.52 PLL test Register (Address:33h)
- 9.2.53 VCO test Register I (Address:34h)
- 9.2.54 RF Analog Test Register (Address: 35h)
- 9.2.55 AES Key data Register (Address: 36h)
- 9.2.56 Channel Select Register (Address: 37h)
- 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0)
- 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1)
- 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2)
- 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3)
- 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4)
- 9.2.58 Data Rate Clock Register (Address: 39h)
- 9.2.59 FCR Register (Address: 3Ah)
- 9.2.60 ARD Register (Address: 3Bh)
- 9.2.61 AFEP Register (Address: 3Ch)
- 9.2.62 FCB Register (Address: 3Dh)
- 9.2.63 KEYC Register (Address: 3Eh)
- 9.2.64 USID Register (Address: 3Fh)
- 10. SPI
- 10.1 SPI Format
- 10.2 SPI Timing Characteristic
- 10.3 SPI Timing Chart
- 10.4 Strobe Commands
- 10.4.1 Strobe Command - Sleep Mode
- 10.4.2 Strobe Command - ldle Mode
- 10.4.3 Strobe Command - Standby Mode
- 10.4.4 Strobe Command - PLL Mode
- 10.4.5 Strobe Command - RX Mode
- 10.4.6 Strobe Command - TX Mode
- ÿþ1 0 . 4 . 7 S t r o b e C o m m a n d F I F O W r i t e P o i n t e r R e s e t
- ÿþ1 0 . 4 . 8 S t r o b e C o m m a n d F I F O R e a d P o i n t e r R e s e t
- ÿþ1 0 . 4 . 9 S t r o b e C o m m a n d D e e p S l e e p M o d e
- 10.5 Reset Command
- 10.6 ID Accessing Command
- 10.7 FIFO Accessing Command
- 11. State machine
- 12. Crystal Oscillator
- 13. System Clock
- 14. Transceiver LO Frequency
- 15. Calibration
- 16. FIFO (First In First Out)
- 17. ADC (Analog to Digital Converter)
- 18. Battery Detect
- 19. Auto-ack and auto-resend
- 20. RC Oscillator
- 21. AES128 Security Packet
- 22. Application circuit
- 23. Abbreviations
- 24. Ordering Information
- 25. Package Information
- 26. Top Marking Information
- 27. Reflow Profile
- 28. Tape Reel Information
- 29. Product Status
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- 新建 Microsoft Word 文档 _3_
LBA7130
Oct., 2012, Version 0.6 (PRELIMINARY) 25 AMICCOM Electronics Corporation
ULS: RX Up/Low side band select. Recommend ULS = [0].
[0]: Up side band, [1]: Low side band.
Refer to section 14.2 for details.
9.2.27 RX Gain Register I (Address: 1Ah)
Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W PRS MIC IGC1 IGC0 MGC1 MGC0 LGC1 LGC0
RX Gain I
R -- MICR IGCR1 IGCR0 MGCR1 MGCR0 LGCR1 LGCR0
PRS: Limiter amplifier discharge manual select. Recommend PRS =[0].
MIC: Mixer buffer gain setting. Recommend MIC =[1].
[0]: 0dB. [1]: 6dB.
IGC [1:0]: IFA Attenuation Select. Recommend IGC =[10].
[00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB.
MGC [1:0]: Mixer Gain Attenuation select. Recommend MGC =[11].
[00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB.
LGC [1:0]: LNA Gain Attenuation select. Recommend LGC =[11].
[00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB.
9.2.28 RX Gain Register II (Address: 1Bh)
Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0
RX Gain II
W
RSAGC1 RSAGC0 VTL2 VTL1 VTL0 VTH2 VTH1 VTH0
RSAGC [1:0]: AGC clock select. Recommend RSAGC = [11].
[00]: IF / 8. [01]: IF/ 4. [10]: IF / 2. [11]: IF
.
VTL [2:0]: VCO tuning voltage lower threshold level setting. Recommend VTL = [000].
[000]: 0.1V. [001]: 0.2V. [010]: 0.3V. [011]: 0.4V.
[100]: 0.5V. [101]: 0.6V. [110]: 0.7V. [111]: 0.8V
VTH [2:0]: VCO tuning voltage upper threshold level setting. Recommend VTH = [010].
[000]: VDD_A – 0.6V. [001]: VDD_A – 0.7V. [010]: VDD_A – 0.8V. [011]: VDD_A – 0.9V
[100]: VDD_A – 1.0V. [101]: VDD_A – 1.1V. [110]: VDD_A – 1.2V. [111]: VDD_A – 1.3V
Remark: VDD_A is on chip analog regulator output voltage where is set to 1.8V.
RH [7:0]: RSSI Calibration High Threshold. (Read only)
9.2.29 RX Gain Register III (Address: 1Ch)
Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R RL7 RL6 RL5 RL4 RL3 RL2 RL1 RL0
RX Gain III
W
-- RDU IFS1 IFS0 RSM1 RSM0 ERSSM RSS
RDU: Clock Generator Select. Recommend RDU = [0].
[0]: 128MHZ [1]: 96MHZ.
IFS [1:0]: IF Frequency Select.
[00]: reserved. [01]: reserved. [10]: reserved [11]: 4MHZ.
RSM [1:0]: RSSI Margin = RTH – RTL. Recommend RSM = [11].
[00]: 5. [01]: 10. [10]: 15. [11]: 20.
Refer to chapter 17 for details.
ERSSM: Ending Mode Select in RSSI Measurement. Recommend ERSSM = [0].
[0]: RSSI ending by RX. [1]: RSSI ending by SYNC_Ok.
RSS: RSSI measurement select. (XADS=0, RSS=0, default mode is thermal sensor.)
[0]: Disable. [1]: Enable (recommend).