User's Manual
Table Of Contents
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- 2. Typical Applications
- 3. Feature
- 4. Pin Configurations
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- I/O
- Function Description
- O
- Connected to a bypass capacitor for RSSI.
- O
- Connected to a bypass capacitor for internal Regulator bias point.
- I
- LNA input. Connected to matching circuit.
- O
- PA input. Connected to matching circuit.
- I
- RF Choke input. Connected to matching circuit.
- I
- VCO supply voltage input.
- O
- Charge-pump. Connected to loop filter.
- I
- PLL supply voltage input.
- I
- Crystal oscillator input.
- O
- Crystal oscillator output.
- I
- SPI chip select.
- I
- SPI clock input pin.
- I
- Connected to a bypass capacitor to supply voltage for digital part.
- I/O
- SPI read/write data.
- G
- Ground
- I/O
- I/O
- O
- I
- Regulator input (External Power Input)
- O
- G
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 5. Pin Description (I: input; O: output, I/O: input or output)
- 6. Chip Block Diagram
- 7. Absolute Maximum Ratings
- 8. Electrical Specification
- 9. Control Register
- 9.1 Control register table
- 9.2 Control register description
- 9.2.1 Mode Register (Address: 00h)
- 9.2.2 Mode Control Register (Address: 01h)
- 9.2.3 Calibration Control Register (Address: 02h)
- 9.2.4 FIFO Register I (Address: 03h)
- 9.2.5 FIFO Register II (Address: 04h)
- 9.2.6 FIFO DATA Register (Address: 05h)
- 9.2.7 ID DATA Register (Address: 06h)
- 9.2.8 RC OSC Register I (Address: 07h)
- 9.2.9 RC OSC Register II (Address: 08h)
- 9.2.10 RC OSC Register III (Address: 09h)
- 9.2.11 CKO Pin Control Register (Address: 0Ah)
- 9.2.12 GIO1 Pin Control Register I (Address: 0Bh)
- 9.2.13 GIO2 Pin Control Register II (Address: 0Ch)
- 9.2.14 Clock Register (Address: 0Dh)
- 9.2.15 PLL Register I (Address: 0Eh)
- 9.2.16 PLL Register II (Address: 0Fh)
- 9.2.17 PLL Register III (Address: 10h)
- 9.2.18 PLL Register IV (Address: 11h)
- 9.2.19 PLL Register V (Address: 12h)
- 9.2.20 Channel Group Register I (Address: 13h)
- 9.2.21 Channel Group Register II (Address: 14h)
- 9.2.22 TX Register I (Address: 15h)
- 9.2.23 TX Register II (Address: 16h)
- 9.2.24 Delay Register I (Address: 17h)
- 9.2.25 Delay Register II (Address: 18h)
- 9.2.26 RX Register (Address: 19h)
- 9.2.27 RX Gain Register I (Address: 1Ah)
- 9.2.28 RX Gain Register II (Address: 1Bh)
- 9.2.29 RX Gain Register III (Address: 1Ch)
- 9.2.30 RX Gain Register IV (Address: 1Dh)
- 9.2.31 RSSI Threshold Register (Address: 1Eh)
- 9.2.32 ADC Control Register (Address: 1Fh)
- 9.2.33 Code Register I (Address: 20h)
- 9.2.34 Code Register II (Address: 21h)
- 9.2.35 Code Register III (Address: 22h)
- 9.2.36 IF Calibration Register I (Address: 23h)
- 9.2.37 IF Calibration Register II (Address: 24h)
- 9.2.38 VCO current Calibration Register (Address: 25h)
- 9.2.39 VCO band Calibration Register I (Address: 26h)
- 9.2.40 VCO band Calibration Register II (Address: 27h)
- 9.2.41 VCO Deviation Calibration Register I (Address: 28h)
- 9.2.42 VCO Deviation Calibration Register II (Address: 29h)
- 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0)
- 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1)
- 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2)
- 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3)
- 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4)
- 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5)
- 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6)
- 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7)
- 9.2.44 VCO Modulation Delay Register (Address: 2Bh)
- 9.2.45 Battery detect Register (Address: 2Ch)
- 9.2.46 TX test Register (Address: 2Dh)
- 9.2.47 Rx DEM test Register I (Address: 2Eh)
- 9.2.48 Rx DEM test Register II (Address: 2Fh)
- 9.2.49 Charge Pump Current Register I (Address: 30h)
- 9.2.50 Charge Pump Current Register II (Address: 31h)
- 9.2.51 Crystal test Register (Address: 32h)
- 9.2.52 PLL test Register (Address:33h)
- 9.2.53 VCO test Register I (Address:34h)
- 9.2.54 RF Analog Test Register (Address: 35h)
- 9.2.55 AES Key data Register (Address: 36h)
- 9.2.56 Channel Select Register (Address: 37h)
- 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0)
- 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1)
- 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2)
- 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3)
- 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4)
- 9.2.58 Data Rate Clock Register (Address: 39h)
- 9.2.59 FCR Register (Address: 3Ah)
- 9.2.60 ARD Register (Address: 3Bh)
- 9.2.61 AFEP Register (Address: 3Ch)
- 9.2.62 FCB Register (Address: 3Dh)
- 9.2.63 KEYC Register (Address: 3Eh)
- 9.2.64 USID Register (Address: 3Fh)
- 10. SPI
- 10.1 SPI Format
- 10.2 SPI Timing Characteristic
- 10.3 SPI Timing Chart
- 10.4 Strobe Commands
- 10.4.1 Strobe Command - Sleep Mode
- 10.4.2 Strobe Command - ldle Mode
- 10.4.3 Strobe Command - Standby Mode
- 10.4.4 Strobe Command - PLL Mode
- 10.4.5 Strobe Command - RX Mode
- 10.4.6 Strobe Command - TX Mode
- ÿþ1 0 . 4 . 7 S t r o b e C o m m a n d F I F O W r i t e P o i n t e r R e s e t
- ÿþ1 0 . 4 . 8 S t r o b e C o m m a n d F I F O R e a d P o i n t e r R e s e t
- ÿþ1 0 . 4 . 9 S t r o b e C o m m a n d D e e p S l e e p M o d e
- 10.5 Reset Command
- 10.6 ID Accessing Command
- 10.7 FIFO Accessing Command
- 11. State machine
- 12. Crystal Oscillator
- 13. System Clock
- 14. Transceiver LO Frequency
- 15. Calibration
- 16. FIFO (First In First Out)
- 17. ADC (Analog to Digital Converter)
- 18. Battery Detect
- 19. Auto-ack and auto-resend
- 20. RC Oscillator
- 21. AES128 Security Packet
- 22. Application circuit
- 23. Abbreviations
- 24. Ordering Information
- 25. Package Information
- 26. Top Marking Information
- 27. Reflow Profile
- 28. Tape Reel Information
- 29. Product Status
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- OIE51402TR_Use manual.pdf
- 新建 Microsoft Word 文档 _3_
LBA7130
Oct., 2012, Version 0.6 (PRELIMINARY) 12 AMICCOM Electronics Corporation
9. Control Register
A7130 contains 69 control registers. MCU can access those control registers via 3-wire (SCS, SCK, SDIO) or 4-wire (SCS,
SCK, SDIO, GIO1/GIO2) SPI interface (max. 15 Mbps). Please refer to Chapter 10 for SPI timing. In general, most of control
registers are just need to configure the recommended values based on A7130 reference code.
9.1 Control register table
Address /
Name
R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W RESETN RESETN RESETN RESETN RESETN RESETN RESETN RESETN00h
Mode
R HECF FECF CRCF CER XER PLLER TRSR TRER
W DDPC ARSSI AIF DFCD WORE FMT FMS ADCM
01h
Mode control
R DDPC ARSSI AIF CD WORE FMT FMS ADCM
02h
Calc
R/W
-- -- -- VCC VBC VDC FBC RSSC
W -- -- -- -- FEP11 FEP10 FEP9 FEP8
R -- -- -- -- LENF11 LENF10 LENF9 LENF8
W FEP7 FEP6 FEP5 FEP4 FEP3 FEP2 FEP1 FEP0
03h
FIFO I
R LENF7 LENF6 LENF5 LENF4 LENF3 LENF2 LENF1 LENF0
04h
FIFO II
W
FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0
05h
FIFO Data
R/W FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0
06h
ID Data
R/W
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0
07h
RC OSC I
R RCOC7 RCOC6 RCOC5 RCOC4 RCOC3 RCOC2 RCOC1 RCOC0
08h
RC OSC II
W
WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0
W
RTCS RCOT2
RCOT1/
RTCC1
RCOT0/
RTCC0
CALWC
RCOSC_E TSEL TWORE
09h
RC OSC III
R
-- -- -- -- CALWR -- -- --
0Ah
CKO Pin
W
ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKOE SCKI
0Bh
GPIO1 Pin I
W
VKM VPM GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1I GIO1OE
0Ch
GPIO2 Pin II
W
BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I GIO2OE
W CGC1 CGC0 GRC3 GRC2 GRC1 GRC0 CGS XS
0Dh
Clock
R IFS1 IFS0 GRC3 GRC2 GRC1 GRC0
-- --
0Eh
PLL I
R/W CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0
W DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 BIP8
0Fh
PLL II
R DBL RRC1 RRC0 CHR3 CHR2 CHR1 CHR0 IP8
W BIP7 BIP6 BIP5 BIP4 BIP3 BIP2 BIP1 BIP0
10h
PLL III
R IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
W BFP15 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 BFP8
11h
PLL IV
R FS YN-FP15 AC14-FP14 AC13-FP13 AC12-FP12 AC11-FP11 AC10-FP10 AC9-FP9 AC8-FP8
W BFP7 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0
12h
PLL V
R AC7-FP7
AC6-FP6 AC5-FP5 AC4-FP4 AC3-FP3 AC2-FP2 AC1-FP1 AC0-FP0
13h
Channel Group I
R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0
14h
Channel Group II
R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0
15h
TX I
W
GDR GF TMDE TXDI TME FDP2 FDP1 FDP0