DSTni-EX User Guide Section Five Part Number 900-335 Revision A 3/04
Copyright & Trademark © 2003 Lantronix, Inc. All rights reserved. Lantronix and the Lantronix logo, and combinations thereof are registered trademarks of Lantronix, Inc. DSTni is a registered trademark of Lantronix, Inc. Ethernet is a registered trademark of Xerox Corporation. All other product names, company names, logos or other designations mentioned herein are trademarks of their respective owners. Am186 is a trademark of Advanced Micro Devices, Inc.
Warranty Lantronix warrants each Lantronix product to be free from defects in material and workmanship for a period specified on the product warranty registration card after the date of shipment. During this period, if a customer is unable to resolve a product problem with Lantronix Technical Support, a Return Material Authorization (RMA) will be issued. Following receipt of an RMA number, the customer shall return the product to Lantronix, freight prepaid.
Contents Copyright & Trademark ________________________________________________________i Warranty___________________________________________________________________ ii Contents___________________________________________________________________ iii List of Tables _______________________________________________________________ iv List of Figures_______________________________________________________________ vi 1: About This User Guide _________________________________________ 1 Intended Audience ____________
Host Mode Operation ________________________________________________________ 50 Sample Host Mode Operations ________________________________________________ 51 USB Pull-up/Pull-down Resistors_______________________________________________ 53 USB Interface Signals _______________________________________________________ 54 5: CAN Controllers _____________________________________________ 55 CANBUS Background _______________________________________________________ 56 Data Exchanges and Communication __________
Table 3-17. Clock Control Register ........................................................................................... 28 Table 3-18. Clock Control Register Definitions.......................................................................... 28 Table 3-19. Extended Slave Address Register ......................................................................... 29 Table 3-20. Extended Slave Address Register Definitions........................................................ 29 Table 3-21.
Table 5-34. Tx/Rx Message Level Register .............................................................................. 71 Table 5-35. Tx/Rx Message Level Register Definitions............................................................. 71 Table 5-36. Interrupt Flags ........................................................................................................ 72 Table 5-37. Interrupt Flag Definitions ........................................................................................
1: About This User Guide This User Guide describes the technical features and programming interfaces of the Lantronix DSTni-EX chip (hereafter referred to as “DSTni”). DSTni is an Application Specific Integrated Circuit (ASIC)-based single-chip solution (SCS) that integrates the leading-edge functionalities needed to develop low-cost, high-performance device server products.
Intended Audience This User Guide is intended for use by hardware and software engineers, programmers, and designers who understand the basic operating principles of microprocessors and their systems and are considering designing systems that utilize DSTni. Conventions This User Guide uses the following conventions to alert you to information of special interest. The symbols # and n are used throughout this Guide to denote active LOW signals. Notes: Notes are information requiring attention.
Organization This User Guide contains information essential for system architects and design engineers. The information in this User Guide is organized into the following chapters and appendixes. Section 1: Introduction Describes the DSTni architecture, design benefits, theory of operations, ball assignments, packaging, and electrical specifications. This chapter includes a DSTni block diagram. Section 2: Microprocessor Describes the DSTni microprocessor and its control registers.
2: SPI Controller This chapter describes the DSTni Serial Peripheral Interface (SPI) controller. Topics include: Theory of Operation on page 4 SPI Controller Register Summary on page 5 SPI Controller Register Definitions on page 6 Theory of Operation SPI Background SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to eight bits) to be shifted into and out of the device at a programmable bit-transfer rate.
When operating as a slave, the SPI clock signal (SCLK) must be slower than 1/8th of the CPU clock (1/16th is recommended). Note: The SPI is fully synchronous to the CLK signal. As a result, SCLK is sampled and then operated on. This results in a delay of 3 to 4 clocks, which may violate the SPI specification if SCLK is faster than 1/8th of the CPU clock. In master mode, the SPI operates exactly on the proper edges, since the SPI controller is generating SCLK.
SPI Controller Register Definitions SPI_DATA Register SPI_DATA is the SPI Controller Data register. Table 2-2. SPI_DATA Register BIT OFFSET 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 B800 /// FIELD RESET RW 11 0 0 0 0 0 0 0 0 0 0 0 RW RW R W RW RW RW RW RW RW RW RW DATA[7:0] 0 0 RW RW 0 0 0 RW RW RW Table 2-3. SPI_DATA Register Definitions Bits 15:8 7:0 Field Name /// DATA[7:0] Description Reserved Always returns zero.
CTL Register CTL is the SPI Controller Control register. Table 2-4. CTL Register 15 14 13 12 11 10 9 8 7 4 3 2 1 0 ALT MSTN WOR CKPOL PHASE /// RW 5 INVCS IRQENB FIELD RESET 6 B802 AUTODRV BIT OFFSET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW R W RW RW RW RW RW RW RW RW RW RW RW Table 2-5.
SPI_STAT Register To clear a bit in the SPI_STAT register, write a 1 to that bit. 14 13 12 11 10 9 8 7 4 3 2 /// COL IRQ /// RW 5 1 0 B804 FIELD RESET 6 SLVSEL 15 OVERRUN BIT OFFSET TXRUN Table 2-6. SPI_STAT Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R Table 2-7.
SPI_SSEL Register SPI_SSEL is the Slave Select Bit Count register. Table 2-8. SPI_SSEL Register BIT OFFSET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 /// RW BCNT[2:0] SELECTO FIELD RESET 0 B806 /// 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 2-9. SPI_SSEL Register Definitions Bits 15:8 7:6 5:1 0 Field Name Description /// Reserved Always returns zero.
DVD_CNTR_LO Register DVD_CNTR_LO is the DVD Counter Low Byte register. Table 2-11. DVD_CNTR_LO Register BIT OFFSET 15 14 13 12 11 10 9 8 7 6 5 4 /// FIELD RESET RW 3 2 1 0 B808 DVDCNT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 RW RW Table 2-12. DVD_CNTR_LO Register Definitions Bits Field Name 15:8 7:0 Description /// Reserved Always returns zero. Divisor Select Selects the SPI clock rate during master mode.
3: I2C Controller This chapter describes the DSTni I2C controller.
Block Diagram Figure 3-1 shows a block diagram of the DSTni I2C controller. Figure 3-1. DSTni I2C Controller Block Diagram Theory of Operation I2C Background 2 The I C bus is a popular serial, two-wire interface used in many systems because of its low overhead. Capable of 100 KHz operation, each device connected to the bus is software addressable by a unique address, with a simple master/slave protocol.
I2C Controller The I2C controller base address is D000h and shares INT2 with the SPI controller. The I2C bus interface requires two bi-directional buffers with open collector (or open drain) outputs and Schmitt inputs.
Table 3-1.
Servicing the Interrupt After servicing this interrupt, and transmitting the second part of the address, the Status register contains one of the codes in Table 3-2. Note: If a repeated START condition transmits, the status code is 10h instead of 08h. Table 3-2.
Transmitting Each Data Byte After each data byte transmits, the IFLG is set, and one of the three status codes in Table 3-3 is in the Status register. Table 3-3.
Table 3-4.
Servicing the Interrupt After servicing this interrupt and transmitting the second part of the address, the Status register contains one of the codes in Table 3-5. Table 3-5.
Receiving Each Data Byte After receiving each data byte, the IFLG is set and one of three status codes in Table 3-6 is in the Status register. When all bytes are received, set the STP bit by writing a 1 to it in the Control register. The I2C controller: Transmits a STOP condition Clears the STP bit Returns to the idle state Table 3-6.
− − − − The IFLG is set and the Status register contains B8h. After the last transmission byte loads in the Data register, clear AAK when IFLG clears. After the last byte is transmitted, the IFLG is set and the Status register contains C8h. The I2C controller returns to the idle state and the AAK bit must be set to 1 before slave mode can be entered again. If the I2C controller does not receive an acknowledge: − − − The IFLG is set. The Status register contains C0h.
Bus Clock Considerations Bus Clock Speed The I2C bus can be defined for bus clock speeds up to 100 Kb/s and up to 400 Kb/s in fast mode. To detect START and STOP conditions on the bus, the M I2C must sample the I2C bus at least 10 times faster than the fastest master bus clock on the bus. The sampling frequency must be at least 1 MHz (4 MHz in fast-mode) to guarantee correct operation with other bus masters. The CLK input clock frequency and the value in CCR bits 2 - 0 determine the I2C sampling frequency.
Resetting the I2C Controller There are two ways to reset the I2C controller. Using the RSTIN# pin Writing to the Software Reset register Using the RSTIN# pin reset method: Clears the Address, Extended Slave Address, Data, and Control registers to 00h. Sets the Status register to F8h. Sets the Clock Control register to 00h. Writing any value to the Software Reset register: Sets the I2C controller back to idle. Sets the STP, STA, and IFLG bits of the Control register to 0.
I2C Controller Register Definitions Slave Address Register Table 3-8. Slave Address Register BIT OFFSET 7 6 5 4 3 2 1 0 D000 FIELD RESET RW 1 1 1 1 0 SLAX9 SLAX8 General Call Address Enable EXTENDED ADDRESS SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GCE 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Table 3-9.
Data Register The Data register contains the transmission data/slave address or the receipt data byte. In transmit mode, the byte is sent most-significant bits first. In receive mode, the first bit received is placed in the register’s most-significant bits. After each byte transmits, the Data register contains the byte present on the bus; therefore, if arbitration is lost, the Data register has the correct receive byte. Table 3-10.
Control Register Table 3-12. Control Register BIT OFFSET FIELD RESET RW 7 6 5 4 3 2 1 0 D004 IEN ENAB STA STP IFLG AAK /// /// 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Table 3-13. Control Register Definitions Bits Field Name Description 7 IEN 6 ENAB 5 STA 4 STP 3 IFLG Extended Slave Address l = interrupt line (INTR) goes HIGH when the IFLG bit is set. 0 = interrupt line remains LOW (default).
Bits Field Name Description 2 AAK Acknowledge 1 = send Acknowledge (LOW level on SDA) during acknowledge clock pulse on the I2C bus if: −The entire 7-bit slave address or the first or second bytes of a 10-bit slave address are received. − The general call address is received and the GCE bit in the ADDR register is set to one. − A data byte is received in master or slave mode. 0 in slave transmitter mode = send Not Acknowledge (HIGH level on SDA) when a data byte is received in master or slave mode.
Table 3-15. Status Register Definitions Bits Field Name Description 7:3 STATUS CODE Status Code Five-bit status code. See Table 3-16. Reserved 2:0 /// Table 3-16.
Clock Control Register The Clock Control register is a Write Only register that contains seven least-significant bits. These least-significant bits control the frequency: At which the I2C bus is sampled. Of the I2C clock line (SCL) when the I2C controller is in master mode. The CPU clock frequency (of CLK) is first divided by a factor of 2N, where N is the value defined by bits 2 – 0 of the Clock Control register. The output of this clock divider is F0.
Extended Slave Address Register Table 3-19. Extended Slave Address Register BIT OFFSET 7 6 5 4 3 2 1 0 D008 FIELD RESET RW SLAX7 SLAX6 SLAX5 SLAX4 SLAX3 SLAX2 SLAX1 SLAX0 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Table 3-20. Extended Slave Address Register Definitions Bits Field Name Description 7 6 5 4 3 2 1 0 SLAX7 SLAX6 SLAX5 SLAX4 SLAX3 SLAX2 SLAX1 SLAX0 Extended slave address. Extended slave address. Extended slave address. Extended slave address. Extended slave address.
4: USB Controller This chapter describes the DSTni Universal Serial Bus (USB) controller. Topics include: Features on page 30 Theory of Operation on page 31 USB Register Summary on page 38 USB Register Definitions on page 39 Host Mode Operation on page 50 Sample Host Mode Operations on page 51 USB Pull-up/Pull-down Resistors on page 53 USB Interface Signals on page 54 Features Fully USB 1.
Theory of Operation USB Background USB is a serial bus operating at 12 Mb/s. USB provides an expandable, hot-pluggable Plugand-Play serial interface that ensures a standard, low-cost socket for adding external peripheral devices. USB allows the connection of up to 127 devices. Devices suitable for USB range from simple input devices such as keyboards, mice, and joysticks, to advanced devices such as printers, scanners, storage devices, modems, and video-conferencing cameras. Version 1.
Microprocessor Interface The USB microprocessor interface is made up of a slave interface and a master interface. The slave interface consists of a number of USB control and configuration registers. USB internal registers can be accessed using a simple microprocessor interface. The master interface is the integrated DMA controller that transfers packet data to and from memory. The DMA controller facilitates USB endpoint data transfer efficiently, while limiting microprocessor involvement.
Figure 4-1. Buffer Descriptor Table The microprocessor manages buffers intelligently for the USB by updating the BDT as necessary. This allows the USB to handle data transmission and reception efficiently while the microprocessor performs communication-overhead processing and other function-dependent applications. Because the microprocessor and the USB share buffers, DSTni uses a simple semaphore mechanism to distinguish who is allowed to update the BDT and buffers in system memory.
Table 4-1. USB Data Direction Device Host Rx Tx OUT or SETUP IN IN OUT or SETUP Addressing BDT Entries Before describing how to access endpoint data via the USB or microprocessor, it is important to understand the BDT addressing mechanism. The BDT occupies up to 256 bytes of system memory. Sixteen bidirectional endpoints can be supported with a full BDT of 256 bytes. Eight bytes are needed for each USB endpoint direction.
Table 4-4.
Table 4-6. USB Buffer Descriptor Format Definitions Bits Field Name Description 7 OWN 6 DATA0/1 5 USB_OWN 4 NINC 3 DTS 1:0 BCH[9:8] 7:0 BCL 7:0 (Bytes 4 through 2 and Low Byte) ADDR[31:0] BD Owner Specifies which unit has exclusive access to the BD. 0 = microprocessor has exclusive and entire BD access; USB ignores all other fields in the BD 1 = USB has exclusive BD access SIE writes a 0 to this bit when it completes a token, except when KEEP=1.
USB Transaction When the USB transmits or receives data: 1. The USB uses the address generation in Table 4-5 to compute the BDT address. 2. After reading the BDT, if the OWN bit equals 1, the SIE DMAs the data to or from the buffer indicated by the BD’s ADDR field. 3. When the TOKEN is complete, the USB updates the BDT and changes the OWN bit to 0 if KEEP is 0. 4. The USB updates the STAT register and sets the TOK_DNE interrupt. 5. When the microprocessor processes the TOK_DNE interrupt: 6.
USB Register Summary Table 4-7. USB Register Summary Hex Offset Mnemonic Register Description 00 02 04 06 INT_STAT ERR_STAT STAT ADDR 08 0A FRM_NUM TOKEN Bits for each interrupt source in the USB. Bits for each error source in the USB. Transaction status in the USB. USB address that the USB decodes in peripheral mode. Contains the 11-bit frame number. Performs USB transactions during host mode. Dedicated to host mode.
USB Register Definitions The following sections provide the USB register definitions. In these sections: The register mnemonic is provided for reference purposes. The register address shown is the address location of the register in the CRB. The initialization value shown is the register’s initialization value at reset. Interrupt Status Register The Interrupt Status register contains bits for each of the interrupt sources in the USB. Each bit is qualified with its respective interrupt enable bits.
Bits Field Name Description 8 USB_RST 7 STALL 6 ATTACH 5 RESUME 4 SLEEP 3 TOK_DNE 2 SOF_TOK 1 ERROR 0 USB_RST Enable/Disable USB_RST Interrupt 1 = enable the USB_RST interrupt. 0 = disable the USB_RST interrupt (default). Stall Used in target and host modes. • In target mode, it asserts when the SIE sends a stall handshake. • In host mode, it is set if the USB detects a stall acknowledge during the handshake phase of a USB transaction.
Error Register The Error register contains bits for each of the error sources in the USB. Each of these bits is qualified with its respective error enable bits. The result is OR’ed together and sent to the ERROR bit of the Interrupt Status register. Once an interrupt bit has been set it may only be cleared by writing a one to the respective interrupt bit. Each bit is set as soon as the error condition is detected.
Bits Field Name Description 5 DMAERR 1 = USB requests a DMA access to read a new BDT, but is not given the bus before USB needs to receive or transmit data. • If processing a TX transfer, this causes a transmit data underflow condition. • If processing an Rx transfer, this causes a receive data overflow condition. This interrupt is useful for developing device-arbitration hardware for the microprocessor and USB to minimize bus request and bus grant latency.
Status Register The Status register reports the transaction status within the USB. When the microprocessor has received a TOK_DNE interrupt, the Status register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOK_DNE interrupt bit is asserted. The Status register is actually a read window into a status FIFO maintained by the USB. When the USB uses a BD, it updates the status register.
Bits Field Name Description 12 RESET 11 HOSTMODE EN 10 RESUME 9 ODD_RST 8 USB_EN 7:4 ENDP 3 TX 2 ODD 1:0 /// USB Reset Signal 1 = enables the USB to generate USB reset signaling. This allows the USB to reset USB peripherals. This control signal is only valid in host mode, (i.e., HOST_MDOE_EN=1). Software must set RESET to 1 for the required amount of time and then clear it to 0 to end reset signaling. For more information about RESET signaling, see Section 7.1.4.
Address Register The Address register contains the unique USB address that the USB decodes in peripheral mode (HOST_MODE_EN=0). In host mode (HOST_MODE_EN=1), the USB transmits this address with a TOKEN packet. This enables the USB to uniquely address any USB peripheral. In either mode the USB_EN bit in the Control register must be set. The register resets to 00h after the reset input activates or the USB decodes a USB reset signal.
Frame Number Registers The Frame Number registers contain the 11-bit frame number. The current frame number is updated in these registers when a SOF_TOKEN is received. Table 4-16. Frame Number Register BIT OFFSET 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 08h FIELD RESET RW 13 /// 0 R 0 R 0 R FRM[10:0] 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Table 4-17.
Token Register The Token register performs USB transactions when in host mode (HOST_MODE_EN=1). When the host microprocessor wants to execute a USB transaction to a peripheral, it writes the TOKEN type and endpoint to this register. After this register is written, the USB begins the specified USB transaction to the address contained in the Address register. The host microprocessor must always check that the TOKEN_BUSY bit in the control register is not set before performing a write to the Token register.
Table 4-18. Token Register BIT OFFSET 15 14 13 12 11 10 9 8 7 6 SOF Threshold Register FIELD 4 3 2 1 0 Token Register CNT[7:0] RESET RW 5 0Ah TOKEN_PID TOKEN_ENDPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W R/ W Table 4-19.
Endpoint Control Registers The Endpoint Control registers contain the endpoint control bits for the 16 endpoints available on USB for a decoded address. These four bits define all the control necessary for any one endpoint. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required by USB for all functions. Therefore, after receiving a USB_RST interrupt, the microprocessor sets ENDPT0 to contain 0Dh. Table 4-21.
Table 4-23. Endpoint Control Register Definitions EP_CTL_DIS EP_RX_EN /// /// /// 1 0 0 0 1 1 1 EP_TX_EN 0 1 0 1 1 Endpoint Enable / Direction Control Disable endpoint. Enable endpoint for TX transfer only. Enable endpoint for RX transfer only. Enable endpoint for RX and TX transfers. Enable endpoint for RX and TX and control (SETUP) transfers. Host Mode Operation A unique feature of the USB core is its host mode logic.
Sample Host Mode Operations Figure 3.
Figure 4.
USB Pull-up/Pull-down Resistors USB uses pull-up or pull-down resistors to determine when an attach or detach event occurs on the bus. Host mode complicates the resistors, since it requires devices to operate as either a USB target device or a USB host. Figure 4-5 shows the two resistor combinations required for USB targets and hosts. Normally, the USB operates in normal mode with HOST_MODE_EN=0. This mode enables resistor R1 and disables the R2 resistors.
USB Interface Signals Clock (CLK) The clock input is required to be connected to a 12 MHz signal that is derived from the USB signals. USP Speed (SPEED) The USB speed indicator is used by external USB transceiver logic to determine which speed interface the USB is implementing. 1 = USB is operating at full speed. 0 = USB is a low-speed device. USB Suspend (SUSPND) The USB suspend signal is used by external logic to determine when the USB is in suspend mode.
5: CAN Controllers This chapter describes the DSTni CAN controller. Topics include: CANBUS Background on page 56 Features on page 57 Theory of Operation on page 58 CAN Register Summaries on page 58 CAN Register Definitions on page 63 CAN Bus Interface on page 84 This chapter assumes you have a working knowledge of the CAN bus protocols. Discussions involving CANBUS beyond the scope of DSTni are not covered in this chapter.
CANBUS Background CAN is a fast and highly reliable, multicast/multimaster, prioritized serial communications protocol that is designed to provide reliable and cost-effective links. CAN uses a twisted-pair cable to communicate at speeds of up to 1 MB/s with up to 127 nodes. It was originally developed to simplify wiring in automobiles. Today, it is often used in automotive and industrialcontrol applications.
CANBUS Speed and Length Table 7-1 shows the relationship between the bit rate and cable length. Table 5-1. Bit Rates for Different Cable Lengths Bit Rate 10 KB/s 20 KB/s 50 KB/s 125 KB/s 250 KB/s 500 KB/s 1 MB/s Cable Length 6.7 km 3.3 km 1.
Theory of Operation The CAN controller appears to the microprocessor as an I/O device. Each peripheral has 256 bytes of I/O address space allocated to it. CAN0 and CAN1 share Interrupt 6. Table 5-2. CAN I/O Address CAN Controller Base Address CAN0 CAN1 A800h A900h CAN Register Summaries DSTni contains two independent CAN channels. Operation and access to each device, however, is the same. The only difference is the starting I/O base address for each channel, as shown in Table 5-2.
Hex Offset 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 Register RxMessage: ID, ID28-13 ID12-00 RxMessage: Data, D55-48, D63-56 D39-32, D47-40 D23-16, D31-24 D07-00, D15-08 RxMessage: RTR, IDE, DLC_3-0,AFI_2-0 RxMessage: Control Flags, Fifo_Lvl_2-0, MsgAval Transmitter and Receive Error Counter Error Status Message Level Threshold Interrupts Flags Interrupt Enable Register CAN mode, Loop_Back, Passive, Run CAN Bit Rate Div.
0x20 0x22 0x24 0x26 0x28 0x2a 0x2e TX Msg 2 /// /// /// /// /// /// TX Msg 2 Ctrl Flags 60 /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// 0x2c /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// D08 D24 D40 D56 /// DLC_0 /// TRX /// /// /// 0x1c /// /// /// /// /// /// /// /// /// DLC_2 D10 D26 D42 D58 /// /// ID13 TRX DLC_0 D08 D24 D40 D56 ID13 ID14 ID15 DLC_3 D11 D27 D43 D59 ID00 ID16 ID14 TXAb
0x4c 0x4e 0x50 CAN Bit Rate Divisor CAN tsegs Acceptance Filter Enable Register /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// 61 /// /// /// /// /// /// /// /// /// /// /// /// /// /// /// tx_er_cnt_0 /// tx_level_0 error_stat_0 /// /// /// /// /// /// /// MsgAval DLC_0 D08 D24 D40 D56 /// int_enable /// DLC_1 D09 D25 D41 D57 DLC_2 D10 D26 D42 D58 /// ID13 ID14 ID15 1 cfg_bitrate_0 Run D12 D28 D44 D60 ID01 ID17 IDE DLC_3 D11 D27 D43 D59 ID0
0x5e 0x60 0x62 0x64 0x66 0x68 0x6a 0x6c 0x6e 0x70 0x72 0x74 116d 0x76 62 frame_bit_3 frame_bit_2 frame_bit_1 frame_bit_0 frame_bit_3 frame_bit_3 frame_bit_2 frame_bit_2 frame_bit_1 frame_bit_1 frame_bit_0 frame_bit_0 ID13 D56 ID13 D56 ID13 D57 RTR ID14 D56 ID13 D57 RTR ID14 D56 ID13 D57 RTR ID14 ID15 ID15 D56 ID13 D57 RTR ID14 D58 IDE 1 D56 D57 RTR ID14 D58 IDE 2 D57 RTR ID14 ID15 3 D58 IDE 4 ID15 D59 ID00 ID16 D59 ID00 ID16 D59 ID00 ID16 D59 ID00 ID16 D59 I
CAN Register Definitions TX Message Registers To avoid priority inversion issues in the transmit path, three transmit buffers are available with a built-in priority arbiter. When a message is transmitted, the priority arbiter evaluates all pending messages and selects the one with the highest priority. The message priority is re-evaluated after each message abort event such as arbitration loss. Figure 5-1.
Tx Message Registers Table 5-5 shows TxMessage_0 registers. The registers for TxMessage_1 and TxMessage_2 are identical except for the offsets. Table 5-5. TxMessage_0:ID28 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 00h OFFSET FIELD ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Table 5-6.
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 /// /// /// /// /// /// Tx Abort Table 5-12. TxMessage_0:Ctrl Flags TRX 0E OFFSET FIELD /// /// /// /// /// /// /// /// Table 5-13. TxMessage_0 Register Definitions Field Name Description ID_28:ID_0 Message Identifier for Both Standard and Extended Messages Standard messages use ID_28 .. ID_18 Message Data Byte 1 is D_63, D_56; Byte 2 is D_55, D_48; and so on.
RX Message Registers A 4-message-deep FIFO stores the incoming messages. Status flags indicate how many messages are stored. Additional flags determine from which acceptance filter the actual message is coming from. RxMessage 3 RxMessage 2 RxMessage 1 uP Bus RxMessage 0 Figure 5-2. RX Message Routing MESSAGE FILTERS CAN Module CAN BUS To read received messages: 1. Wait for rx_msg interrupt. 2. MessageReadLoop: 3.
Rx Message Registers The following table shows RxMessage registers. See the complete register table at the start of this section. Table 5-14. RxMessage:ID28 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 30h OFFSET FIELD RESET ID28 0 ID27 0 ID26 0 ID25 0 ID24 0 ID23 0 ID22 0 ID21 0 ID20 0 ID19 0 ID18 0 ID17 0 ID16 0 ID15 0 ID14 0 ID13 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-15.
Table 5-20. Rx Message: Data 39 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 36h OFFSET FIELD RESET D39 0 D38 0 D37 0 D36 0 D35 0 D34 0 D33 0 D32 0 D47 0 D46 0 D45 0 D44 0 D43 0 D42 0 D41 0 D40 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-21. Rx Message: Data 39 Register Definitions Bits Field Name Description 15:0 D[39:40] Message Data Table 5-22.
Table 5-26. RxMessage: RTR BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RTR 0 IDE 0 DLC_3 0 DLC_2 0 DLC_1 0 DLC_0 0 R/W R/W R/W R/W R/W R/W R/W R/W 3C OFFSET /// 0 FIELD RESET 0 0 0 AFI_2 AFI_1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W AFI_0 0 R/W /// 0 Table 5-27. Rx Message: RTR Register Definitions Bits Field Name 15:11 10:8 Description /// Reserved Acceptance Filter Indicator Indicates which acceptance filter(s) accepted the incoming message.
Error Count and Status Registers Table 5-30. Tx/Rx Error Count BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 40h OFFSET FIELD RESET RE7 0 RE6 0 RE5 0 RE4 0 RE3 0 RE2 0 RE1 0 RE0 0 TE7 0 TE6 0 TE5 0 TE4 0 TE3 0 TE2 0 TE1 0 TE0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-31.
Table 5-34. Tx/Rx Message Level Register BIT 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 0 0 0 0 0 0 /// 0 0 0 0 0 0 RL1 0 RL0 0 TL1 0 TL0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FIELD RESET R/W 7 44h OFFSET Table 5-35.
Interrupt Flags The following flags are set on internal events (they activate an interrupt line when enabled). They are cleared by writing a ‘ 1’ to the appropriate flag. Acknowledging the tx_msg interrupt also acknowledges all tx_xmit interrupt sources. Acknowledging one of the tx_xmit interrupt sources also acknowledges the tx_msg interrupt. Note: The reset value of this register’s bits is indeterminate.
Interrupt Enable Registers All interrupt sources are grouped into three groups (traffic, error and diagnostics interrupts). To enable a particular interrupt, set its enable flag to ‘ 1’ . Table 5-38.
Bits Field Name Description 3 OVR_LOAD 2 ARB_LOSS 1 0 INT_ENB Overload Condition− int3n group (diagnostic interrupts) 1 = enable flag set. 0 = enable flag not set. Arbitration Loss− int3n group (diagnostic interrupts) 1 = enable flag set. 0 = enable flag not set. Reserved General Interrupt Enable 1 = enable flag set. 0 = enable flag not set. /// CAN Operating Mode The CAN modules can be used in different operating modes.
Figure 5-3. CAN Operating Mode DSTni CAN Module 1 CAN Module 2 a b c d CAN Port 1 CAN Port 2 Note: The Loopback Mode register in CAN module 2 is not functional. For proper operation in loopback mode, the configuration of both CAN modules must be the same. CAN Configuration Registers The following registers set bit rate and other configuration parameters. Table 5-42.
Table 5-44. Configuration Register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4Eh OFFSET EDGE_MOD CFG_SJW1 SAMP_MOD AUTO_RES TS1_0 TS1_1 TS1_2 TS1_3 TS2_0 TS2_1 /// 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET R/W TS2_2 OVR_MSG FIELD Table 5-45.
The following relations exist for bit time, time quanta, time segments ½, and the data sampling point. Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships Bit Time 1 tseg1 + 1 time quanta (TQ) tseg2 + 1 Sample Point Bittime = (1+ ( tseg1 + 1) + (tseg2 + 1)) x timequanta timequanta = (bitrate +1) / fclk e.g.
Acceptance Filter and Acceptance Code Mask Three programmable Acceptance Mask and Acceptance Code register (AMR/ACR) pairs filter incoming messages. The acceptance mask register (AMR) defines whether the incoming bit is checked against the acceptance code register (ACR). Table 5-46.
10 9 8 7 6 5 4 3 2 1 0 RTR 11 IDE 12 ID00 13 ID01 14 ID02 15 ID03 BIT ID04 Table 5-50. Acceptance Mask Register: ID 12 /// 54h OFFSET RESET R/W ID05 ID06 ID07 ID08 ID09 ID10 ID11 ID12 FIELD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-51.
Table 5-54. Acceptance Code Register 15 14 13 12 11 10 9 8 7 RESET R/W 5 4 3 2 1 0 ID13 ID14 ID15 ID16 ID17 ID18 ID19 ID21 ID22 ID23 ID24 ID25 ID26 ID27 ID28 FIELD 6 58h ID20 BIT OFFSET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5-55. Acceptance Code Register Definitions Bits Field Name Description 15:0 ID[28:13] Incoming Bit Check 1 = incoming bit is “don’ t care.
CANbus Analysis Three additional registers are provided for advanced analysis of a CAN system. These registers include arbitration lost and error capture registers, as well as a CANbus frame reference register that contains information about the CANbus state and the physical Rx and TX pins. Arbitration Lost Capture Register The Arbitration Lost Capture register captures the most recent arbitration loss event with the frame reference pointer. Table 5-60.
Error Capture Register The Error Capture register captures the most recent error event with the frame reference pointer, rx- and tx-mode and the associated error code. Table 5-62.
Frame Reference Register The Frame Reference register contains information of the current bit of the CAN message. A frame reference pointer indicates the current bit position. This enables message tracing on bit level. Note: The reset value of this register’s bits is indeterminate. Table 5-64.
Bits Field Name Description 5:0 FRB[5:0] frame_ref_bit_nr A 6-bit vector that counts the bit numbers in one field. Example: if field = “data” = “01010”, “bit_nr” = “000000”, and “tx_mode” = ‘1’, it indicates that the first data bit is being transmitted. CAN Bus Interface DSTni contains two complete CAN controllers, CAN0 and CAN1. Each controller supplies two signal pins, CAN receive (CAN_RX) and CAN transmit (CAN_TX).
You can also provide local isolated power for the transceiver circuits, as required when using CANopen. If you are using both DeviceNet and CANopen, use the jumpers to select between bus power (+5_BUS) or isolated power (ISO_PWR). The jumpers P_C05V and P_C0G will then provide +5_CAN and GND_CAN to the transceiver circuits. Note: Diagrams are for tutorial purposes only and may not reflect the actual circuit on the evaluation module.
Figure 5-8. CAN Transceiver and Isolation Circuits +5v(F) C12 0.01uf R190 680 U19 8 7 5 C68 0.01uf 2 6 CAN_RX +5_CAN 1 VCC 3 GND GND_CAN 4 HCPL-0601 U18 R189 C67 GND_CAN +3.3v C9 0.01uf R193 270 CAN_TX 0.01uf U6 1 2 VCC RXD 0.
87
