User Manual
Table Of Contents
- Chapter 1: Product Overview 1
- Chapter 2: Configuration & Testing 19
- Chapter 3: Development Environment 27
- Product Overview
- Introduction
- Performance Specifications
- Electrical Interface
- Pin Functions
- Pin 1 (VIN)
- Pin 2 (LPP TX) and Pin 3 (LPP RX)
- Pin 4 (DIGITAL_IO1) and Pin 11 (DIGITAL_IO2)
- Pin 5 (ANALOG_IN1) and Pin 10 (ANALOG_IN2)
- Pins 6 and 7 (GND)
- Pin 8 (LOW_RF_POWER)
- Pin 9 (PWR_DN)
- Pin 12 (TPP RX) and Pin 13 (TPP TX)
- Pin 14 (3.3V_Logic_supply)
- USB Programming Cable
- USB Cable Installation
- Antennas
- External Antenna
- On-board Antenna
- Additional Specifications
- Dimensions: Gridstream S4SBR 25-1681 / 25-1682
- Dimensions: Gridstream S4SBR 25-1683 / 25-1684
- Configuration & Testing
- Development Environment
- Gridstream SCADA/DA Series 4 Single Board Radio Interface Board
- Transparent Port (TPP) Connection
- LAN Packet Port (LPP) Connection
- Onboard Regulator
- Digital Input
- Analog Input
- General Usage Instruction
- Gridstream S4SBR Logic
- Control Register 1
- Control Register 2
- Digital I/O Functionality
- Analog Input Functionality
- Memory Location
- Manufacturer Contact Information
- External Antenna Specifications
- Ground Plane Specifications
- RF External Antenna Cable Specifications
- External Antenna Radiation Pattern
- Identifying a Reverse-Polarity Connector
- Specifications
- On-board Antenna Radiation Pattern
- FCC Class B
- RF Exposure
- Industry Canada
- Host FCC Label Requirement
- Data Sheets
- Whip Antenna P/N 16-1000-0
- RF External Antenna Cable P/N 21-1000-0
Landis+Gyr Chapter 3 - Development Environment
Gridstream SCADA/DA S4SBR 98-1138 Rev AD 31
• If Control = “1” - Analog to Digital Channel => Read channel at 7704h (2 bytes) and report
A2-Output
Pin A2 at 7701h (Bits 4-6), if 7701 (Bit 0 = “1”) Output then read Control at 7701h (Bit 6)
• If Control = “0” - General Purpose => Set state at 7701h (Bit 5) and report
• If Control = “1” - Analog to Digital Channel => Report Error in configuration
Digital I/O Functionality
NOTE: This device provides two general purpose digital I/O lines. These are controllable through
the DCW programming language. It is outside the scope of this document to describe that
language but, in brief, there are mechanisms by which each line can be independently configured
as input or output.
The state of inputs can be read, and the state of outputs can be set. DCW code execution operates
as
a virtual environment and, as such, does not support rapid transitions. Users should understand
the speed limitations associated with the use of these digital I/O pins.
The register below can be used to control either of the two general purpose I/O pins (D1 & D2)
located at memory location 7700 (hex).
Table 3 - 1. Control Register 1
Bit Feature Description Dflt.
0 Pin D1 Direction
0: Input
1: Output
0
1Pin D1 State
When D1, bit 0 is "0" and bit 2-3 is "00", then bit 1 returns current state
as "0" or "1".
When D1, bit 0 is "0" and bit 2-3 is not "00", then read location 7706-
7709 which returns the count of the as defined in bit 2-3.
When D1, bit 0 is "1" then the value can be read or set.
0
2-3 Pin D1 Control
00: General Purpose I/O
01: Count interrupts on rising edge
10: Count interrupts on falling edge
11: Count interrupts on either edge
0
4 Pin D2 Direction
0: Input
1: Output
0
5Pin D2 State
When D2, bit 4 is "0" then bit 5 returns current state as "0" or "1".
When D2, bit 4 is "1" then the value can be read or set.
0
6-7 Reserved N/A 0
draft 29 Jan 2013