User Manual
Table Of Contents
- Chapter 1: Product Overview 1
- Chapter 2: Configuration & Testing 19
- Chapter 3: Development Environment 27
- Product Overview
- Introduction
- Performance Specifications
- Electrical Interface
- Pin Functions
- Pin 1 (VIN)
- Pin 2 (LPP TX) and Pin 3 (LPP RX)
- Pin 4 (DIGITAL_IO1) and Pin 11 (DIGITAL_IO2)
- Pin 5 (ANALOG_IN1) and Pin 10 (ANALOG_IN2)
- Pins 6 and 7 (GND)
- Pin 8 (LOW_RF_POWER)
- Pin 9 (PWR_DN)
- Pin 12 (TPP RX) and Pin 13 (TPP TX)
- Pin 14 (3.3V_Logic_supply)
- USB Programming Cable
- USB Cable Installation
- Antennas
- External Antenna
- On-board Antenna
- Additional Specifications
- Dimensions: Gridstream S4SBR 25-1681 / 25-1682
- Dimensions: Gridstream S4SBR 25-1683 / 25-1684
- Configuration & Testing
- Development Environment
- Gridstream SCADA/DA Series 4 Single Board Radio Interface Board
- Transparent Port (TPP) Connection
- LAN Packet Port (LPP) Connection
- Onboard Regulator
- Digital Input
- Analog Input
- General Usage Instruction
- Gridstream S4SBR Logic
- Control Register 1
- Control Register 2
- Digital I/O Functionality
- Analog Input Functionality
- Memory Location
- Manufacturer Contact Information
- External Antenna Specifications
- Ground Plane Specifications
- RF External Antenna Cable Specifications
- External Antenna Radiation Pattern
- Identifying a Reverse-Polarity Connector
- Specifications
- On-board Antenna Radiation Pattern
- FCC Class B
- RF Exposure
- Industry Canada
- Host FCC Label Requirement
- Data Sheets
- Whip Antenna P/N 16-1000-0
- RF External Antenna Cable P/N 21-1000-0
Chapter 1 - Product Overview Landis+Gyr
6 98-1138 Rev AD Gridstream SCADA/DA S4SBR
Pin Functions
Pin Outs for the connector as described below are designed to interface with developer OEM
architecture. When pins are connected to non developer boards or when standard interfaces are
required without use of the USB cable (P/N 19-2325, as shown in Figure 1 - 6), appropriate design
constraints (power and logic level) must be adhered to (See “Gridstream SBR Logic” on page 30).
Figure 1 - 3. Pinout Diagram (Rear View) For All Board Versions)
Table 1 - 4. I/O Connector Pin Functions and Acceptable Voltage Levels
Pin
Number
Name Function
Logic
Level Low
(VDC)
Logic Level
High (VDC)
1 VIN Main supply for the board. 0
4.0 ~ 7.0
Nominal =
5.0
2 LPP TX
This pin is an output from the device for connecting to
RadioShop via the LAN Packet Port (LPP) interface.
0 ~ 0.5 2.8 ~ 3.4
3 LPP RX
This pin is an input to the device for connecting to
RadioShop via the LAN Packet Port (LPP) interface.
0 ~ 0.6 2.6 ~ 3.4
4 DIGITAL_IO1
A general purpose Digital Input / Output Pin. The application-
specific DCW can use this pin as desired.
0 ~ 0.6 2.6 ~ 3.4
5ANALOG_IN1
An input to the device’s A/D converter. The application-
specific DCW can read the voltage on this pin. Note: This pin
may be configured as a Digital I/O, if desired.
0 ~ 2.5
6 and 7 GND
Common ground for both power and communications. These
two pins are tied together on the device.
00
8 LOW_RF_POWER
Digital input used to select Low-Power Mode, an RF output
power reduction to 100 mW [20 dBm].
ground 3.3V max
9 PWR_DN Digital input used to completely shut down the device. ground 2.8 ~ 5V max
10 ANALOG_IN2
An input to the device’s A/D converter. The application-
specific DCW can read the voltage on this pin. Note: This pin
may be configured as a Digital I/O, if desired.
0 ~ 2.5
11 DIGITAL_IO2
A general purpose Digital Input / Output Pin. The application-
specific DCW can use this pin as desired.
0 ~ 0.6 2.6 ~ 3.4
12 TPP RX This pin is an input to the Transparent Port (TPP) device. 0 ~ 0.6 2.6 ~ 3.4
13 TPP TX This pin is an output from the Transparent Port (TPP) device. 0 ~ 0.5 2.8 ~ 3.4
14 3.3V_Logic_supply
3.3V Supply for logic level shifting. Pin is current limited to
300μA
≈3.3
draft 29 Jan 2013