User's Manual

TiWi-SL MODULE
DATASHEET
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330-0085-R0.4 Copyright © 2011 LS Research, LLC Page 25 of 36
SPI Clock Switching Characteristics
This interface only supports single block reads and writes.
SPI/WSPI
Parameter Min Max Unit
f
clock
Clock frequency, CLK C
L
< 15pF 0 48 ns
DC Low/high duty cycle
C
L
< 15pF
40 60 ns
t
TLH
Rise time, CLK
C
L
< 15pF
4.3 ns
t
THL
Fall time, CLK
C
L
< 15pF
3.5
ns
t
ISU
Setup time, input valid before CLK↑
C
L
< 15pF
3.5
ns
t
IH
Hold time, input valid after CLK↑
C
L
< 15pF
5
ns
t
ODLY
Setup time, input valid before CLK↑
C
L
< 15pF
4 15
ns
t
setupSPI_CSx
CSn Delay time, CLK↑ to output invalid
C
L
< 15pF
5.5
ns
Over recommended operating conditions (See Figure 14)
Table 15: SPI Clock Switching Characteristics
Figure 14: SPI Interface Clock Timing