User's Manual

TiWi-SL MODULE
DATASHEET
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330-0085-R0.4 Copyright © 2011 LS Research, LLC Page 24 of 36
SPI Data Switching Characteristics
Parameter Min Max Unit
t
CS
Delay time, CS↓to DIN read/write command valid 0 clock cycles
t
busy
(1)
Fixed busy delay till DOUT data valid 32 224 clock cycles
t
EC
Delay time, DOUT data valid to CS↑ 0 clock cycles
t
DB
(2)
Data block size 32 clock cycles
Over recommended operating conditions (See Figure 12, Figure 13)
(1)The busy delay can be configured as fixed value after the address de-assertion. The values can be 1 to 7 (in multiples of 32 clock cycles).
(2) The data length can be configured as 16 or 32-bit words.
Table 14: SPI Data Switching Characteristics
Figure 12: SPI Interface Read Timing
Figure 13: SPI Interface Write Timing