User's Manual
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ORDERING INFORMATION
- MODULE ACCESSORIES
- BLOCK DIAGRAM
- FUNCTIONAL BLOCK FEATURES
- TIWI-SL MODULE FOOTPRINT AND PIN DEFINITIONS
- PIN DESCRIPTIONS
- ELECTRICAL SPECIFICATIONS
- DEVICE POWER-UP AND ENABLE
- SPI HOST-CONTROLLER INTERFACE
- SOLDERING RECOMMENDATIONS
- CLEANING
- OPTICAL INSPECTION
- REWORK
- SHIPPING, HANDLING, AND STORAGE
- AGENCY CERTIFICATIONS
- AGENCY STATEMENTS
- OEM RESPONSIBILITIES TO COMPLY WITH FCC AND INDUSTRY CANADA REGULATIONS
- OEM LABELING REQUIREMENTS FOR END-PRODUCT
- OEM END PRODUCT USER MANUAL STATEMENTS
- MECHANICAL DATA
- DEVICE MARKINGS
- CONTACTING LS RESEARCH
TiWi-SL MODULE
DATASHEET
The information in this document is subject to change without notice.
Confirm the data is current by downloading the latest revision from www.lsr.com.
330-0085-R0.4 Copyright © 2011 LS Research, LLC Page 21 of 36
Clock Polarity
Data is sampled on the falling edge of the clock as shown in Figure 9.
Shared SPI Bus Mode
This section describes the solution for a system in which the SPI host controller interfaces with other
SPI-compatible devices.
The topology includes one SPI master and an SPI bus shared by several slaves. The bus topology has
a single master (Host) and multiple slaves. The following lines are common to all SPI devices in the
system:
• CLK
• Data IN
• Data OUT—when this line is shared between the different devices, it must be set to go to a 3-
state output when /CS is de-asserted via the vendor-specific command,
HCI_VS_TI_SPI_Configuration (refer to TBD)
Figure 8 illustrates the shared SPI bus architecture, depicting three devices as examples.
Figure 8: Shared SPI Bus Topology