User's Manual
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ORDERING INFORMATION
- MODULE ACCESSORIES
- BLOCK DIAGRAM
- FUNCTIONAL BLOCK FEATURES
- TIWI-SL MODULE FOOTPRINT AND PIN DEFINITIONS
- PIN DESCRIPTIONS
- ELECTRICAL SPECIFICATIONS
- DEVICE POWER-UP AND ENABLE
- SPI HOST-CONTROLLER INTERFACE
- SOLDERING RECOMMENDATIONS
- CLEANING
- OPTICAL INSPECTION
- REWORK
- SHIPPING, HANDLING, AND STORAGE
- AGENCY CERTIFICATIONS
- AGENCY STATEMENTS
- OEM RESPONSIBILITIES TO COMPLY WITH FCC AND INDUSTRY CANADA REGULATIONS
- OEM LABELING REQUIREMENTS FOR END-PRODUCT
- OEM END PRODUCT USER MANUAL STATEMENTS
- MECHANICAL DATA
- DEVICE MARKINGS
- CONTACTING LS RESEARCH
TiWi-SL MODULE
DATASHEET
The information in this document is subject to change without notice.
Confirm the data is current by downloading the latest revision from www.lsr.com.
330-0085-R0.4 Copyright © 2011 LS Research, LLC Page 20 of 36
Read Operation: to Host Data Transfer
Figure 7 shows the SPI read transaction timing.
Figure 7: SPI Read Transaction
SPI Header:
Read = Opcode for write is 0x03
SMSB, SLSB = 16-bit data payload length (including alignment byte)
Busy = Busy byte (0x00)
SPI Payload (equal to the HCI command + padding byte):
D(0) … D(n), 0x00 (depending on the number of bytes in SPI payload)
In order for the total SPI packet (that is, the SPI transaction) to be 16-bit aligned, the HCI event sent
from the device is padded with an additional 0x00 byte (if required). Refer to for more information. The
device signals to the host its desire to transfer data by asserting the /IRQ line. The host asserts /CS
and drives the following 3 bytes to DI line: READ opcode followed by two BUSY bytes. The device will
then drive the data on the DO line. The first two bytes will indicate the payload length, and immediately
after that, the data payload bytes will follow. Upon completing the read transaction, the host must de-
assert /CS. The Bluetooth device then de-asserts its /IRQ line immediately as a response (within ≤ 250
ns).
NOTE
The host interrupt input should be set to trigger on high to low edge.
The read transaction is performed according to the following parameters:
• A single SPI read transaction includes a full HCI packet.
• The number of bytes for each SPI transaction will always be even.
• The padded byte is added at the end of the HCI packet, but is not reflected in the HCI header
length parameter (H4 packet length ignores this byte).
• The host should read a full SPI packet (including the alignment byte) according to the SPI
packet length (SMSB and SLSB).
• The host must ignore the additional byte according to the HCI packet length.
Refer to Section “SPI Timing Information” for the SPI read and write timing diagrams.