User's Manual
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ORDERING INFORMATION
- MODULE ACCESSORIES
- BLOCK DIAGRAM
- FUNCTIONAL BLOCK FEATURES
- TIWI-SL MODULE FOOTPRINT AND PIN DEFINITIONS
- PIN DESCRIPTIONS
- ELECTRICAL SPECIFICATIONS
- DEVICE POWER-UP AND ENABLE
- SPI HOST-CONTROLLER INTERFACE
- SOLDERING RECOMMENDATIONS
- CLEANING
- OPTICAL INSPECTION
- REWORK
- SHIPPING, HANDLING, AND STORAGE
- AGENCY CERTIFICATIONS
- AGENCY STATEMENTS
- OEM RESPONSIBILITIES TO COMPLY WITH FCC AND INDUSTRY CANADA REGULATIONS
- OEM LABELING REQUIREMENTS FOR END-PRODUCT
- OEM END PRODUCT USER MANUAL STATEMENTS
- MECHANICAL DATA
- DEVICE MARKINGS
- CONTACTING LS RESEARCH
TiWi-SL MODULE
DATASHEET
The information in this document is subject to change without notice.
Confirm the data is current by downloading the latest revision from www.lsr.com.
330-0085-R0.4 Copyright © 2011 LS Research, LLC Page 18 of 36
The host must assert /CS (that is, drive the signal to low) to indicate that it is about to write to the
device. Consequently, the device will assert the /IRQ line when it is ready to receive the data and after
completing its wake-up sequence. The host will wait for the /IRQ line to be asserted and then will start
driving the data on the DI line. Data on the DI line consist of a 5-byte header followed by the data
payload.
The first byte of the header is the WRITE opcode, followed by two bytes that indicate the size of the
payload length (including the alignment byte). Two BUSY bytes will then follow to conclude the header.
Directly following the last byte of the header will be the data payload.
When the device detects the HCI packet header, it de-asserts its /IRQ line during the packet data.
When the host completes the SPI transaction, it must de-assert its /CS line.
SPI Header:
Write = Opcode for write is 0x01
MMSB, MLSB = 16-bit data payload length (including alignment byte)
Busy = Busy byte (0x00)
SPI Payload (equal to the HCI command + padding byte):
D(0) … D(n), 0x00 (depending on the number of bytes in SPI payload)
XX = Should be ignored by master
In order for the total SPI packet (that is, the SPI transaction) to be 16-bit aligned, the HCI command
must be padded with an additional 0x00 byte if the HCI packet is even size. Refer to Table 12 for more
information.
SPI Header SPI Payload Padding Byte
5 bytes Odd None
5 bytes Even 0x00
Table 12: SPI Read/Write Transaction: 16-bit Alignment
The write transaction is performed according to the following parameters:
• A complete HCI packet must be included within every SPI transaction.
• Pausing and resuming the SPI clock: the host may stop driving the SPI CLK during the SPI
packet. During this time, /CS will remain asserted. Upon resuming the SPI CLK the Host will
not send the header again and will simply continue driving the data from the point it was
previously stopped.
• The number of bytes for each SPI transaction is always even.
• The padding byte is added at the end of the HCI packet, but is not reflected in the HCI header
length parameter (H4 packet length ignores this byte).
• The device ignores the additional byte.