User's Manual

Table Of Contents
TiWi-SL MODULE
DATASHEET
The information in this document is subject to change without notice.
Confirm the data is current by downloading the latest revision from www.lsr.com.
330-0085-R0.4 Copyright © 2011 LS Research, LLC Page 16 of 36
SPI HOST-CONTROLLER INTERFACE
This section describes the Serial Peripheral Interface ( SPI™) Host-Controller interface (HCI).
Overview
The SPI interface provides high-speed data transfer capability with low power consumption for mobile
electronic devices. The SPI bus was designed to operate on a point-to-multipoint basis by providing a
separate, active-low chip select (CS) per device.
Supported SPI Features
SPI supports the following features:
Point-to-multipoint
Supported clock rates = 26MHz and 38.4MHz
The device interface is always an SPI Slave, host is always an SPI Master
SPI Interface Description
In order to facilitate a broad implementation, the protocol is half duplex and does not require
simultaneous operation of data OUT (DO) and data IN (DI). All TI communication devices are slaves in
this protocol, and all transactions are initiated by the host, as the SPI Master. The clock rate for each
one of the connected devices may be different and configured per device.
Figure 4 illustrates the SPI interface signals; Table 11 describes the SPI interface signals.
Host
Device
SPI_CLK
SPI_CS
SPI_IRQ
SPI_DO (Data Out)
SPI_DI (Data In)
Figure 4: SPI Interface Signals