User's Manual

SSD50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
27
© Copyright 2015 Laird. All Rights Reserved
Americas: [phone]
Europe: [phone]
Hong Kong: [phone]
Pin #
Name
Type
Voltage
Reference
Description
If Not
Used
64
XPABIAS21
O
VDDIO
Control signal for external 2GHz power
amplifier Chain 1.
N/C
65-
80
GND
-
-
Thermal Ground Pad
(Important for RF performance and
thermal dissipation; please flow the
reference design)
GND
Integration Considerations
The following Wi-Fi information should be taken into consideration when integrating the SSD50NBT:
 When WLAN is communicating via the SDIO bus, the internal switch regulator (1.2V out) can be used to
power SSD50NBT itself. Pin-47 (VDD12_PMU) of SSD50NBT is the internal PMU output pin that generates
1.2V to provide to AVDD12 (pin-43), DVDD12 (pin-44), and AVDD12_USB (pin-45).
 When WLAN is communicating via the USB bus, an external 1.2 V (maximum rating 400 mA) is needed for
to AVDD12 (pin-43), DVDD12 (pin-44), and AVDD12_USB (pin-45). This is due to insufficient power from
internal PMU.
 No matter WLAN is running at SDIO or USB bus, a 10uF, 6.3V low ESR capacitor is always needed directly on
pin-47 (VDD12_PMU) as close as possible to the pin.
BOOT STRAPS OPTIONS FOR WI-FI INTERFACE
SSD50NBT provides either SDIO or USB interface for WLAN connection. It is configured per the table below
Table 18: Wi-Fi interface configuration table
Pin No.
Pin Name
SDIO 2.0
USB 2.0
Note
41
SD_CMD
H
L
-
39
SDIO_DATA_2
H
L
-
38
SDIO_DATA_1
H
H
10KΩ Pull High to Avoid Booting into test mode.
Note: It is implemented inside the SSD50NBT. No
external pull “H” is needed.
3
GPIO_10
L
L
10K Ω Pull “L” to Avoid leakage.
61
DEBUG_UART_TXD
N/C
H
No connection at SDIO bus.
52
WLAN_TDO
H
L
10K Ω Pull “H” to Avoid leakage. Only SDIO