User's Manual

SSD50NBT
Hardware Integration Guide
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Feature
Description
System Clocking
(RTC Block)
The SSD50NBT has an RTC block which controls the clocks and power going to other internal modules.
Its inputs consist of sleep requests from these modules and its outputs consists of clock enable and
power signals which are used to gate the clocks going to these modules. The RTC block also manages
resets going to other modules with the device. The SSD50NBT’s clocking is grouped into two types:
high-speed and low-speed.
High Speed Clocking
The reference 26 MHz clock source inside the SSD50NBT drives the PLL and RF synthesizer of Wi-Fi and
Bluetooth. To minimize power consumption, the reference clock source is powered off in SLEEP,
HOST_OFF, and OFF states.
Low Speed Clocking
On WiFi operation, SSD50NBT do not need an external sleep clock source. Instead, an internal ring
oscillator is used to generate a low frequency sleep clock. It is also used to run the state machines and
counters related to low power states. The SSD50NBT has an internal calibration module which
produces a 32.768 KHz output with minimal variation. For this, it uses the reference clock source as
the golden clock. As a result, the calibration module adjusts for process and temperature variations in
the ring oscillator when the system is in ON state.
The BT section sharing clock from wifi chip. It will not able to get into deep sleep mode without 32KHz
present at pin-24. Without get into deep sleep mode, it will consume 3.3mA at VDD_BT supply. In
order to have BT get into deep sleep mode, a 32.768KHz slow clock is must on pin-24. When
32.768KHz present on pin-24, BT chip can go into deep sleep mode with 0.08mA current consume on
VDD_BT supply.
Interface Clock
The host interface clock represents another clock domain for the SSD50NBT. This clock comes from the
SDIO and is independent from the other internal clocks. It drives the host interface logic as well as
certain registers which can be accessed by the host in HOST_OFF and SLEEP states.
MAC/BB/RF Block
The SSD50NBT Wireless MAC consists of five major blocks:
 Host interface unit (HIU) for bridging to the AHB for bulk data accesses and APB for register
accesses
 Ten queue control units (QCU) for transferring TX data
 Ten DCF control units (DCU) for managing channel access
 Protocol control unit (PCU) for interfacing to baseband
DMA receive unit (DRU) for transferring RX data
Baseband Block
The SSD50NBT baseband module (BB) is the physical layer controller for the 802.11b/g/n air interface.
It is responsible for modulating data packets in the transmit direction and detecting and demodulating
data packets in the receive direction. It has a direct control interface to the radio to enable hardware
to adjust analog gains and modes dynamically.
Clock Sharing
Clock sharing is implemented on the SSD50NBT. The Bluetooth chip (CSR8811) receives a reference
clock from Wi-Fi chip (QCA6004). When Wi-Fi is in power off/reset state, Bluetooth is also off.
32.768KHz slow clock is needed for BT to get into deep sleep mode.