User's Manual

SSD50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/bluetooth
11
© Copyright 2015 Laird. All Rights Reserved
Americas: [phone]
Europe: [phone]
Hong Kong: [phone]
Feature
Description
Reset Control
WLAN_PWD_L and BT_PWD_L pins must be asserted low to reset Wi-Fi and Bluetooth. After these
signals are de-asserted, the radio waits for host communication. Until then, all modules except the
host interface are held in reset.
Once the host has initiated communication, the radio turns on its crystal and then the PLL. After all
clocks are stable and running, the block resets are automatically de-asserted.
Note: Because it derives its clock from WLAN, the Bluetooth function should be powered down/reset
whenever WLAN is reset.
Reset Sequence
After a COLD_RESET event, the SSD50NBT enters the HOST_OFF state and awaits communication from
the host. From that point, the typical COLD_RESET sequence is shown below:
 When the host is ready to use the radio, it initiates communication via the SDIO.
 The radio enters the WAKEUP state and then the ON state. Embedded software configures the
radio functions and interfaces. When the radio is ready to receive commands from the host, it
sets an internal function ready bit.
 The host reads the ready bit and sends function commands to the radio.
 The embedded CPU may continue to be held in reset under some circumstances until its reset is
cleared by an external pin or when the host clears a register.
Power Transition
Integrated power management and control functions and low power operation for maximum battery
life across all operational states by:
 Gating clocks for logic when not needed
 Shutting down unneeded high speed clock sources
 Reducing voltage levels to specific blocks in some states
See Error! Reference source not found..
Figure 1: Power state transition