User's Manual

Laird SSD45N
Hardware Integration Guide, version 0.01
Figure 2: Power on/down timing
Figure 3: Reset timing
Description Minimum (µsec)
T
a
Time between VBAT, VDD33, and I/O supplies valid and 1.8 V supply
valid
1
0
T
b
Time between 1.8 V supply valid and CHIP_PWD_L deassertion 5
T
c
Time between CHIP_PWD_L assertion and 1.8 V supply invalid 0
T
d
Time between 1.8 V supply invalid and VBAT, VDD33, and I/O supplies
invalid
N/A
2
T
e
Length of CHIP_PWDP_L pulse 5
[1] Supply valid represents the voltage level has reached 90% level.
[2] No strict requirements. This parameter can also be negative.
SSD40NBT and SSD45N Pin Comparison Table
Pin
#
Pin Name
Pin Name
Pin
#
Pin Name
Pin Name
SSD40NBT
SSD45N
SSD40NBT
SSD45N
1
GND
GND
31
RSVD
VDD33
2
GND
RF_IN-OUT
32
VDDIO
VDD33
3
GND
GND
33
WL_LED_ACT
DVDD_SDIO
4
GND
GND
34
WL_GPIO_1
GND
5
ANT_2
GND
35
SYS_RST_L
CLK32K
6
GND
GND
36
CHIP_PWD_L
GND
7
GND
GND
37
RSVD
BT_CLK_OUT
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