User's Manual
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ORDERING INFORMATION
- MODULE ACCESSORIES
- BLOCK DIAGRAM
- DEVELOPMENT KIT
- MODULE PINOUT AND PIN DESCRIPTIONS
- MODULE OVERVIEW
- OPERATING MODES TRUTH TABLE
- MODES OF OPERATION
- DEVELOPMENT TOOLS
- ELECTRICAL SPECIFICATIONS
- SOLDERING RECOMMENDATIONS
- CLEANING
- OPTICAL INSPECTION
- REWORK
- SHIPPING, HANDLING, AND STORAGE
- AGENCY STATEMENTS
- MECHANICAL DATA
- COMPATIBILITY
- MODULE REVISION HISTORY
- CONTACTING LS RESEARCH
SiFLEX02-HP TRANSCEIVER MODULE
DATASHEET
The information in this document is subject to change without notice.
Confirm the data is current by downloading the latest revision from www.lsr.com.
330-0047-R0.7 Copyright © 2010-2011 LS Research, LLC Page 11 of 35
Figure 5 ATXMEGA256A3 Block Diagram
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is
more code efficient while achieving throughputs many times faster than conventional single-
accumulator or CISC based microcontrollers.