User's Manual
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ORDERING INFORMATION
- MODULE ACCESSORIES
- BLOCK DIAGRAM
- DEVELOPMENT KIT
- MODULE PINOUT AND PIN DESCRIPTIONS
- MODULE OVERVIEW
- OPERATING MODES TRUTH TABLE
- MODES OF OPERATION
- DEVELOPMENT TOOLS
- ELECTRICAL SPECIFICATIONS
- SOLDERING RECOMMENDATIONS
- CLEANING
- OPTICAL INSPECTION
- REWORK
- SHIPPING, HANDLING, AND STORAGE
- AGENCY STATEMENTS
- MECHANICAL DATA
- COMPATIBILITY
- MODULE REVISION HISTORY
- CONTACTING LS RESEARCH
SiFLEX02-HP TRANSCEIVER MODULE
DATASHEET
The information in this document is subject to change without notice.
Confirm the data is current by downloading the latest revision from www.lsr.com.
330-0047-R0.7 Copyright © 2010-2011 LS Research, LLC Page 10 of 35
MODULE OVERVIEW
Figure 4 shows the internal interconnects of the ICs on the SiFLEX02-HP module. Consult the
respective IC datasheets for details, or contact LSR sales to purchase the SiFLEX02-HP module
schematics as part of LSR’s ModFLEX™ design program. For a high-level block diagram of the
SiFLEX02-HP module, see Figure 1.
Atmel
ATXMEGA256A3
/RST
RX_START
/SEL
MOSI
MISO
SCLK
SLP_TR
IRQ
DIG3 (TX EN)
DIG4 (RX EN)
RF
Power Amplifier /
LNA /
TX/RX Switches
PA/LNA
Power Supply
26
27
28
29
30
31
32
33
Atmel
AT86RF212
8
10
24
11
23
22
20
19
1
2
DIG1 (ANT_SW)
9
50
ANT_SEL
VPA_AD
6
Antenna 1
Antenna 2
Supply Voltage
59
VGE
Figure 4 SiFLEX02-HP Module Block Diagram – Internal Interconnects
Microcontroller
The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR® enhanced RISC architecture. By executing powerful instructions
in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million Instructions Per
Second (MIPS), thus allowing the system designer to optimize power consumption versus processing
speed. Figure 5 shows a block diagram of the ATXMEGA256A3.