User's Manual

LoRa/BLE Modules
Hardware Integration Guide
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These signals operate according to normal industry convention. UART_RX, UART_TX, UART_CTS, UART_RTS are
all CMOS logic levels that track VCC. For example, when RX and TX are idle they sit at a high logic level (VCC).
Conversely for handshaking pins CTS, RTS at 0 V is treated as an assertion.
The module communicates with the customer application using the following signals (Figure 4):
 Port /TXD of the application sends data to the module’s UART_RX signal line
 Port /RXD of the application receives data from the module’s UART_TX signal line
Figure 4: UART Signals
Note: The RM1xx serial module output is at CMOS logic levels that track VCC. Level conversion must be
added to interface with an RS-232 level compliant interface.
Some serial implementations link CTS and RTS to remove the need for handshaking. Laird does not recommend
linking CTS and RTS other than for testing and prototyping. If these pins are linked and the host sends data at the
point that the RM1xx deasserts its RTS signal, then there is significant risk that internal receive buffers will
overflow, which could lead to an internal processor crash. This will drop the connection and may require a
power cycle to reset the module. Laird recommends that the correct CTS/RTS handshaking protocol be adhered
to for proper operation.
Table 14: UART Interface
Signal Name
Pin #
I/O
Comments
SIO_21/UART_TX
2
O
SIO_21 (alternative function UART_TX) is an output, set high (in FW).
SIO_22/UART_RX
3
I
SIO_22 (alternative function UART_RX) is an input, set with internal pull-
up (in FW).
SIO_23/UART_RTS
4
O
SIO_23 (alternative function UART_RTS) is an output, set low (in FW).
SIO_24/UART_CTS
5
I
SIO_24 (alternative function UART_CTS) is an input, set with internal pull-
down (in FW).
The UART interface is also used to load customer developed smartBASIC application script.
SPI Bus
The SPI interface is an alternate function on SIO pins, configurable by smartBASIC.
The module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CSB is implemented
using any spare SIO digital output pins to allow for multi-dropping.
The SPI interface enables full duplex synchronous communication between devices. It supports a three-wire
(SPI_MOSI, SPI_MISO, SPI_SCK,) bidirectional bus with fast data transfers to and from multiple slaves. Individual
chip select signals are necessary for each of the slave devices attached to a bus, but control of these is left to the
application through use of SIO signals. I/O data is double buffered.
The SPI peripheral supports SPI mode 0, 1, 2, and 3.