User's Manual

LoRa/BLE Modules
Hardware Integration Guide
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Clocks and Timers
Clocks
The integrated high accuracy (+/-20 ppm) 32.768 kHz crystal oscillator provides protocol timing and helps with
radio power consumption in the system Standby Doze/Deep sleep modes by reducing the time that the RX
window needs to be open. Standard accuracy clocks tend to have lower accuracy +/-250 ppm.
The integrated high accuracy 16 MHz (+/-10 ppm) crystal oscillator helps with radio operation and also helps
reduce power consumption in the active modes.
Timers
In keeping with the event-driven paradigm of smartBASIC, the timer subsystem enables smartBASIC applications
to be written which allow future events to be generated based on timeouts.
Regular Timer – There are eight built-in timers (regular timers) derived from a single RTC clock which are
controlled solely by smart BASIC functions. The resolution of the regular timer is 976 microseconds.
Tick Timer – A 31-bit free running counter that increments every 1 millisecond. The resolution of this
counter is 488 microseconds. This counter can be accessed using the functions GetTickCount() and
GetTickSince().
Refer to the smart BASIC user guide for more information.
Memory for smartBASIC Application Code
User has up to TBD Kbytes of data memory available for smart BASIC application script.
RF
865 – 870MHz (250 – 11000 bps over the air data rate)
RM186 protocol can optionally employs 50kbps FSK when enabled by the gateway
RM191 Lora radio: 902 – 928MHz (980 – 21900 bps over the air data rate)
Bluetooth Low Energy radio: 2402–2480MHz (1Mbps over the air data rate).
BLE TX output power of +3dBm programmable (via smartBASIC command) to -20dBm in steps of 4dB.
BLE TX Whisper mode1 -30dBm (via smartBASIC command).
BLE TX Whisper mode2 -55dBm (via smartBASIC command).
BLE Receiver (with integrated channel filters) to achieve maximum sensitivity -91dBm @ 1Mbps BLE.
BLE Antenna: Integrated monopole chip antenna on RM1xx
UART Interface
The Universal Asynchronous Receiver/Transmitter offers fast, full-duplex, asynchronous serial communication
with built-in flow control support (UART_CTS, UART_RTS) in HW. Parity checking is supported.
UART_TX, UART_RX, UART_RTS, and UART_CTS form a conventional asynchronous serial data port with
handshaking. The interface is designed to operate correctly when connected to other UART devices such as the
16550A. The signaling levels are CMOS logic levels that track VCC, and are inverted with respect to the signaling
on an RS232 cable.
Two-way hardware flow control is implemented by UART_RTS and UART_CTS. UART_RTS is an output and
UART_CTS is an input. Both are active low.